From 8477866a13b6b1d5266854d14cfd72a5ba8ff058 Mon Sep 17 00:00:00 2001
From: Gabe Black <gabeblack@google.com>
Date: Wed, 19 Aug 2020 03:03:53 -0700
Subject: [PATCH] dev,arm: Stop using TheISA in ARM specific files.

These can use ArmISA since there's no ambiguity about what ISA is being
used with those files.

Change-Id: I02e8ea0ab70215679eb939adaa949400e878b1ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32928
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/arm/isa/insts/neon64.isa      |  2 +-
 src/arch/arm/isa/templates/sve_mem.isa | 16 ++++++++--------
 src/dev/arm/generic_timer.cc           |  2 +-
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa
index 5186de38c..b9729a160 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -46,7 +46,7 @@ let {{
     smallFloatTypes = ("uint32_t",)
 
     zeroSveVecRegUpperPartCode = '''
-        TheISA::ISA::zeroSveVecRegUpperPart(%s,
+        ArmISA::ISA::zeroSveVecRegUpperPart(%s,
             ArmStaticInst::getCurSveVecLen<uint64_t>(xc->tcBase()));
     '''
 
diff --git a/src/arch/arm/isa/templates/sve_mem.isa b/src/arch/arm/isa/templates/sve_mem.isa
index 896b95c6e..b5c2dc0ba 100644
--- a/src/arch/arm/isa/templates/sve_mem.isa
+++ b/src/arch/arm/isa/templates/sve_mem.isa
@@ -146,7 +146,7 @@ def template SveContigLoadExecute {{
         %(op_rd)s;
         %(ea_code)s;
 
-        TheISA::VecRegContainer memData;
+        ArmISA::VecRegContainer memData;
         auto memDataView = memData.as<MemElemType>();
 
         %(rden_code)s;
@@ -203,7 +203,7 @@ def template SveContigLoadCompleteAcc {{
         %(op_decl)s;
         %(op_rd)s;
 
-        TheISA::VecRegContainer memData;
+        ArmISA::VecRegContainer memData;
         auto memDataView = memData.as<MemElemType>();
 
         if (xc->readMemAccPredicate()) {
@@ -233,7 +233,7 @@ def template SveContigStoreExecute {{
         %(op_rd)s;
         %(ea_code)s;
 
-        TheISA::VecRegContainer memData;
+        ArmISA::VecRegContainer memData;
         auto memDataView = memData.as<MemElemType>();
 
         %(wren_code)s;
@@ -270,7 +270,7 @@ def template SveContigStoreInitiateAcc {{
         %(op_rd)s;
         %(ea_code)s;
 
-        TheISA::VecRegContainer memData;
+        ArmISA::VecRegContainer memData;
         auto memDataView = memData.as<MemElemType>();
 
         %(wren_code)s;
@@ -929,7 +929,7 @@ def template SveStructLoadExecute {{
         %(op_rd)s;
         %(ea_code)s;
 
-        TheISA::VecRegContainer memData;
+        ArmISA::VecRegContainer memData;
         auto memDataView = memData.as<Element>();
 
         if (fault == NoFault) {
@@ -984,7 +984,7 @@ def template SveStructLoadCompleteAcc {{
         %(op_decl)s;
         %(op_rd)s;
 
-        TheISA::VecRegContainer memData;
+        ArmISA::VecRegContainer memData;
         auto memDataView = memData.as<Element>();
 
         memcpy(memData.raw_ptr<uint8_t>(), pkt->getPtr<uint8_t>(),
@@ -1017,7 +1017,7 @@ def template SveStructStoreExecute {{
         %(op_rd)s;
         %(ea_code)s;
 
-        TheISA::VecRegContainer memData;
+        ArmISA::VecRegContainer memData;
         auto memDataView = memData.as<Element>();
 
         %(wren_code)s;
@@ -1054,7 +1054,7 @@ def template SveStructStoreInitiateAcc {{
         %(op_rd)s;
         %(ea_code)s;
 
-        TheISA::VecRegContainer memData;
+        ArmISA::VecRegContainer memData;
         auto memDataView = memData.as<Element>();
 
         %(wren_code)s;
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index a620eec6c..da8de08bd 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -1273,7 +1273,7 @@ GenericTimerMem::GenericTimerMem(GenericTimerMemParams *const p)
 void
 GenericTimerMem::validateFrameRange(const AddrRange &range)
 {
-    fatal_if(range.start() % TheISA::PageBytes,
+    fatal_if(range.start() % ArmISA::PageBytes,
              "GenericTimerMem::validateFrameRange: Architecture states each "
              "register frame should be in a separate memory page, specified "
              "range base address [0x%x] is not compliant\n");
-- 
2.30.2