From 849fd62cfed9b6623865c7af76dd1bfbc6adf457 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 6 Feb 2014 01:00:11 +0100 Subject: [PATCH] Added counters sat test case --- tests/sat/counters.v | 35 +++++++++++++++++++++++++++++++++++ tests/sat/counters.ys | 10 ++++++++++ 2 files changed, 45 insertions(+) create mode 100644 tests/sat/counters.v create mode 100644 tests/sat/counters.ys diff --git a/tests/sat/counters.v b/tests/sat/counters.v new file mode 100644 index 000000000..09e273044 --- /dev/null +++ b/tests/sat/counters.v @@ -0,0 +1,35 @@ + +module counter1(clk, rst, ping); + input clk, rst; + output ping; + reg [31:0] count; + + always @(posedge clk) begin + if (rst) + count <= 0; + else + count <= count + 1; + end + + assign ping = &count; +endmodule + +module counter2(clk, rst, ping); + input clk, rst; + output ping; + reg [31:0] count; + + integer i; + reg carry; + + always @(posedge clk) begin + carry = 1; + for (i = 0; i < 32; i = i+1) begin + count[i] <= !rst & (count[i] ^ carry); + carry = count[i] & carry; + end + end + + assign ping = &count; +endmodule + diff --git a/tests/sat/counters.ys b/tests/sat/counters.ys new file mode 100644 index 000000000..330895f82 --- /dev/null +++ b/tests/sat/counters.ys @@ -0,0 +1,10 @@ + +read_verilog counters.v +proc; opt + +expose -shared counter1 counter2 +miter -equiv -make_assert -make_outputs counter1 counter2 miter + +cd miter; flatten; opt +sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs + -- 2.30.2