From 84ba92ed750ce7b4183f6c2054dbf60d498053c6 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 9 May 2018 17:56:03 +0100 Subject: [PATCH] arch-arm: S3____ are Implementation defined In the AArch64 ISA, S3____ refers to a pool of implementation defined registers, provided that reg numbers are in the following range: is in the range 0 - 7 can take the values 11, 15 is in the range 0 - 15 is in the range 0 - 7 Change-Id: I7edd013e5cea4887f5e4c5a81f4835b7de93bd50 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/10501 Maintainer: Andreas Sandberg --- src/arch/arm/miscregs.cc | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index e1ddbf9d3..08e37bb70 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -2082,9 +2082,12 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, } break; } - break; + M5_FALLTHROUGH; + default: + // S3__11__ + return MISCREG_IMPDEF_UNIMPL; } - break; + M5_UNREACHABLE; case 12: switch (op1) { case 0: @@ -2370,7 +2373,8 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, } break; } - break; + // S3__15__ + return MISCREG_IMPDEF_UNIMPL; } break; } -- 2.30.2