From 84c726e240a912ec95ec3f26b7660bf0a5c47637 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 20 Jun 2022 13:12:35 +0100 Subject: [PATCH] --- openpower/sv/vector_ops.mdwn | 33 ++++----------------------------- 1 file changed, 4 insertions(+), 29 deletions(-) diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn index d22dfb5bc..ce947543f 100644 --- a/openpower/sv/vector_ops.mdwn +++ b/openpower/sv/vector_ops.mdwn @@ -13,7 +13,6 @@ Links: * [[simple_v_extension/specification/bitmanip]] previous version, contains pseudocode for sof, sif, sbf - The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVX512 conflictd for example. This section includes such examples. Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors) Notes: @@ -236,35 +235,11 @@ Example vmsof.m v2, v3, v0.t 0 1 x x x x 0 0 v2 content -Pseudo-code: - - def sof(rd, rs1, rs2): - rd = 0 - setting_mode = rs2 == x0 or (regs[rs2] & 1) - - while i < XLEN: - bit = 1<