From 84cc389c01390fa3ecf2ddf2ad6e227586e81232 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 15 Sep 2020 21:19:51 +0100 Subject: [PATCH] do not need FAST regs in MMU --- src/soc/fu/mmu/pipe_data.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/soc/fu/mmu/pipe_data.py b/src/soc/fu/mmu/pipe_data.py index 2c2a45ca..1b7066d4 100644 --- a/src/soc/fu/mmu/pipe_data.py +++ b/src/soc/fu/mmu/pipe_data.py @@ -19,7 +19,6 @@ class MMUInputData(IntegerData): regspec = [('INT', 'ra', '0:63'), # RA ('INT', 'rb', '0:63'), # RB ('SPR', 'spr1', '0:63'), # MMU (slow) - ('FAST', 'fast1', '0:63'), # MMU (fast: LR, CTR etc) ] def __init__(self, pspec): super().__init__(pspec, False) @@ -31,7 +30,6 @@ class MMUInputData(IntegerData): class MMUOutputData(IntegerData): regspec = [('INT', 'o', '0:63'), # RT ('SPR', 'spr1', '0:63'), # MMU (slow) - ('FAST', 'fast1', '0:63'), # MMU (fast: LR, CTR etc) ] def __init__(self, pspec): super().__init__(pspec, True) -- 2.30.2