From 84d314f73d640784deee843da281dded2e8f70c3 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 6 May 2022 11:45:31 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index cdc077698..4eee357e4 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -446,4 +446,8 @@ CPUs were about the same rate. DRAM bitcells *simply cannot exceed these rates*, yet the pressure from Software Engineers is to make *sequential* algorithm processing faster and faster because parallelising of algorithms is simply too difficult to master and always -has been. +has been. Thus whilst DRAM has to go parallel (like RAID Striping) to +keep up, CPUs are now at 8-way Multi-Issue 5 ghz clock rates and +are at an astonishing four levels of cache (L1 to L4). The amount +of wiring inside such CPUs is now measured in miles. + -- 2.30.2