From 84e18a7a473bcff64b73c43cce71353f5c2d3307 Mon Sep 17 00:00:00 2001
From: Gabe Black <gabe.black@gmail.com>
Date: Tue, 3 Nov 2020 20:54:01 -0800
Subject: [PATCH] mips: Fix the build after the MMU changes.

Change-Id: I2bd1a6a8607fe1da056182ca840036db35b53c36
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36995
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/mips/isa/decoder.isa  | 8 ++++----
 src/arch/mips/isa/includes.isa | 1 +
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 3b2b0156e..e5613f52b 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -738,7 +738,7 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x01: tlbr({{
                         MipsISA::PTE *PTEntry =
                             dynamic_cast<MipsISA::TLB *>(
-                                xc->tcBase()->getITBPtr())->
+                                xc->tcBase()->getMMUPtr()->itb)->
                                 getEntry(Index & 0x7FFFFFFF);
                         if (PTEntry == NULL) {
                             fatal("Invalid PTE Entry received on "
@@ -819,7 +819,7 @@ decode OPCODE_HI default Unknown::unknown() {
                             (1 << newEntry.AddrShiftAmount) - 1;
 
                         auto ptr = dynamic_cast<MipsISA::TLB *>(
-                            xc->tcBase()->getITBPtr());
+                            xc->tcBase()->getMMUPtr()->itb);
                         Config3Reg config3 = Config3;
                         PageGrainReg pageGrain = PageGrain;
                         int SP = 0;
@@ -885,7 +885,7 @@ decode OPCODE_HI default Unknown::unknown() {
                             (1 << newEntry.AddrShiftAmount) - 1;
 
                         auto ptr = dynamic_cast<MipsISA::TLB *>(
-                            xc->tcBase()->getITBPtr());
+                            xc->tcBase()->getMMUPtr()->itb);
                         Config3Reg config3 = Config3;
                         PageGrainReg pageGrain = PageGrain;
                         int SP = 0;
@@ -909,7 +909,7 @@ decode OPCODE_HI default Unknown::unknown() {
                             vpn = ((EntryHi >> 11) & 0xFFFFFFFC);
                         }
                         tlbIndex = dynamic_cast<MipsISA::TLB *>(
-                            xc->tcBase()->getITBPtr())->
+                            xc->tcBase()->getMMUPtr()->itb)->
                             probeEntry(vpn, entryHi.asid);
                         // Check TLB for entry matching EntryHi
                         if (tlbIndex != -1) {
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 53b10558c..34922e4cf 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -76,6 +76,7 @@ output exec {{
 #include "arch/mips/dt_constants.hh"
 #include "arch/mips/faults.hh"
 #include "arch/mips/isa_traits.hh"
+#include "arch/mips/mmu.hh"
 #include "arch/mips/mt.hh"
 #include "arch/mips/mt_constants.hh"
 #include "arch/mips/pagetable.hh"
-- 
2.30.2