From 84f5f3c4238e7a79bd758d6e8a0a81495cf26aa0 Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 23 Aug 2019 08:37:59 +0000 Subject: [PATCH] back.pysim: don't crash when trying to drive a nonexistent domain clock. --- nmigen/back/pysim.py | 4 ++++ nmigen/test/test_sim.py | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py index 25189d7..8471b51 100644 --- a/nmigen/back/pysim.py +++ b/nmigen/back/pysim.py @@ -451,6 +451,10 @@ class Simulator: for domain_obj in self._domains: if not domain_obj.local and domain_obj.name == domain: clk = domain_obj.clk + break + else: + raise ValueError("Domain '{}' is not present in simulation" + .format(domain)) def clk_process(): yield Passive() yield Delay(phase) diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py index e7d759d..c9cdcb7 100644 --- a/nmigen/test/test_sim.py +++ b/nmigen/test/test_sim.py @@ -413,6 +413,13 @@ class SimulatorIntegrationTestCase(FHDLTestCase): msg="Domain 'sync' already has a clock driving it"): sim.add_clock(1) + def test_add_clock_wrong(self): + m = Module() + with self.assertSimulation(m) as sim: + with self.assertRaises(ValueError, + msg="Domain 'sync' is not present in simulation"): + sim.add_clock(1) + def test_eq_signal_unused_wrong(self): self.setUp_lhs_rhs() self.s = Signal() -- 2.30.2