From 84f9cd0025b080c7b1fc2dc86aaacc08a8f88805 Mon Sep 17 00:00:00 2001 From: C-Elegans Date: Mon, 16 Jan 2017 10:16:03 -0500 Subject: [PATCH] Optimize compares to powers of 2 Remove opt_compare and put comparison pass in opt_expr assuming a [7:0] is unsigned a >= (1<= 0 becomes constant true, a < 0 becomes constant false delete opt_compare.cc revert opt.cc to commit b7cfb7dbd (remove opt_compare step) --- passes/opt/Makefile.inc | 1 - passes/opt/opt.cc | 2 - passes/opt/opt_compare.cc | 78 --------------------------------------- passes/opt/opt_expr.cc | 61 ++++++++++++++++++++++++++++++ 4 files changed, 61 insertions(+), 81 deletions(-) delete mode 100644 passes/opt/opt_compare.cc diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc index a15c4184d..a8b1537bb 100644 --- a/passes/opt/Makefile.inc +++ b/passes/opt/Makefile.inc @@ -6,7 +6,6 @@ OBJS += passes/opt/opt_reduce.o OBJS += passes/opt/opt_rmdff.o OBJS += passes/opt/opt_clean.o OBJS += passes/opt/opt_expr.o -OBJS += passes/opt/opt_compare.o ifneq ($(SMALL),1) OBJS += passes/opt/share.o diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc index b689be480..021c1a03f 100644 --- a/passes/opt/opt.cc +++ b/passes/opt/opt.cc @@ -128,7 +128,6 @@ struct OptPass : public Pass { { while (1) { Pass::call(design, "opt_expr" + opt_expr_args); - Pass::call(design, "opt_compare"); Pass::call(design, "opt_merge" + opt_merge_args); design->scratchpad_unset("opt.did_something"); Pass::call(design, "opt_rmdff" + opt_rmdff_args); @@ -142,7 +141,6 @@ struct OptPass : public Pass { else { Pass::call(design, "opt_expr" + opt_expr_args); - Pass::call(design, "opt_compare"); Pass::call(design, "opt_merge -nomux" + opt_merge_args); while (1) { design->scratchpad_unset("opt.did_something"); diff --git a/passes/opt/opt_compare.cc b/passes/opt/opt_compare.cc deleted file mode 100644 index 15b547e6f..000000000 --- a/passes/opt/opt_compare.cc +++ /dev/null @@ -1,78 +0,0 @@ -#include "kernel/yosys.h" -#include "kernel/sigtools.h" -#include "kernel/utils.h" -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN -void replace_le_cell(Cell* cell, Module* module){ - RTLIL::SigSpec a = cell->getPort("\\A"); - RTLIL::SigSpec b = cell->getPort("\\B"); - RTLIL::SigSpec y(RTLIL::State::S0, cell->parameters["\\Y_WIDTH"].as_int()); - if(b.is_fully_const() && b.is_fully_zero() ){ - if(cell->parameters["\\A_SIGNED"].as_bool()){ - // a < 0, can be replaced with a[MAX_BIT] - log("Found x < 0 (signed), replacing with the last bit\n"); - int a_width = cell->parameters["\\A_WIDTH"].as_int(); - if(a_width > 0){ - y[0] = a[a_width-1]; - module->connect(cell->getPort("\\Y"), y); - module->remove(cell); - } - } - } -} -void replace_ge_cell(Cell* cell, Module* module){ - RTLIL::SigSpec a = cell->getPort("\\A"); - RTLIL::SigSpec b = cell->getPort("\\B"); - RTLIL::SigSpec y = cell->getPort("\\Y"); - if(b.is_fully_const() && b.is_fully_zero()){ - if(cell->parameters["\\A_SIGNED"].as_bool()){ - log("Found x >= 0 (signed), optimizing\n"); - RTLIL::SigSpec a_prime(RTLIL::State::S0, cell->parameters["\\Y_WIDTH"].as_int()); - int a_width = cell->parameters["\\A_WIDTH"].as_int(); - if(a_width > 0){ - a_prime[0] = a[a_width-1]; - module->remove(cell); - module->addNot("$not", a_prime, y,false); - } - } - } -} -void optimize_compares(Design* design, Module* module){ - log_header(design, "Executing OPT_COMPARE pass.\n"); - log_push(); - TopoSort> cells; - for(auto cell: module->cells()) - if(design->selected(module,cell) && cell->type[0] == '$'){ - cells.node(cell); - } - cells.sort(); - for (auto cell: cells.sorted){ - if (cell->type == "$lt"){ - replace_le_cell(cell,module); - } - else if(cell->type == "$ge"){ - replace_ge_cell(cell,module); - } - } - -} -struct OptCompare : public Pass { - OptCompare() : Pass("opt_compare") {} - virtual void execute(vector, Design* design){ - for(auto module: design->selected_modules()) - optimize_compares(design,module); - } - virtual void help() { - log("\n"); - log("opt_compare\n"); - log("\n"); - log("This pass optimizes some signed compares with 0.\n"); - log("In particular, it replaces a < 0 with the msb of a,\n"); - log("and a >= 0 with the inverted msb of a.\n"); - log("\n"); - - } -} OptCompare; - - -PRIVATE_NAMESPACE_END diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index b62eae285..b629ed326 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -1166,6 +1166,67 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } } + //replace a <0 or a >=0 with the top bit of a + if(do_fine && (cell->type == "$lt" || cell->type == "$ge")) + { + bool is_lt = cell->type == "$lt" ? 1 : 0; + RTLIL::SigSpec a = cell->getPort("\\A"); + RTLIL::SigSpec b = cell->getPort("\\B"); + int a_width = cell->parameters["\\A_WIDTH"].as_int(); + //replace a(signed) < 0 with the high bit of a + if(b.is_fully_const() && b.is_fully_zero() && cell->parameters["\\A_SIGNED"].as_bool() == true){ + RTLIL::SigSpec a_prime(RTLIL::State::S0, cell->parameters["\\Y_WIDTH"].as_int()); + a_prime[0] = a[a_width-1]; + if(is_lt){ + log("Optimizing a < 0 with a[%d]\n",a_width - 1); + module->connect(cell->getPort("\\Y"), a_prime); + module->remove(cell); + } + else{ + log("Optimizing a >= 0 with ~a[%d]\n",a_width - 1); + module->addNot("$not", a_prime, cell->getPort("\\Y")); + module->remove(cell); + } + did_something = true; + goto next_cell; + } + else if(b.is_fully_const() && b.is_fully_def() && cell->parameters["\\A_SIGNED"].as_bool() == false){ + int b_value = b.as_int(false); + if(b_value == 0){ + RTLIL::SigSpec a_prime(RTLIL::State::S0,1); + if(is_lt){ + log("replacing a(unsigned) < 0 with constant false\n"); + a_prime[0] = RTLIL::State::S0; + } + else{ + log("replacing a(unsigned) >= 0 with constant true\n"); + a_prime[0] = RTLIL::State::S1; + } + module->connect(cell->getPort("\\Y"), a_prime); + module->remove(cell); + did_something = true; + goto next_cell; + } + else if((b_value & -b_value) == b_value){ //if b has only 1 bit set + int bit_set = ceil_log2(b_value); + RTLIL::SigSpec a_prime(RTLIL::State::S0,a_width-bit_set); + for(int i = bit_set; i < a_width; i++){ + a_prime[i-bit_set] = a[i]; + } + if(is_lt){ + log("replacing a < %d with !a[%d:%d]\n",b_value,a_width-1,bit_set); + module->addLogicNot("$logic_not", a_prime,cell->getPort("\\Y")); + } + else{ + log("replacing a >= %d with |a[%d:%d]\n",b_value,a_width-1,bit_set); + module->addReduceOr("$reduce_or", a_prime,cell->getPort("\\Y")); + } + module->remove(cell); + did_something = true; + goto next_cell; + } + } + } next_cell:; #undef ACTION_DO -- 2.30.2