From 84ffef7369bff65a60034ed847d3813ea8bc9c90 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 29 Jul 2016 13:59:33 -0700 Subject: [PATCH] Add an RVC test --- isa/Makefile | 2 + isa/macros/scalar/test_macros.h | 36 -------- isa/rv64mi/breakpoint.S | 3 +- isa/rv64mi/ma_addr.S | 7 +- isa/rv64uc/Makefrag | 11 +++ isa/rv64uc/rvc.S | 151 ++++++++++++++++++++++++++++++++ 6 files changed, 171 insertions(+), 39 deletions(-) create mode 100644 isa/rv64uc/Makefrag create mode 100644 isa/rv64uc/rvc.S diff --git a/isa/Makefile b/isa/Makefile index 95092e8..b836bbd 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -7,6 +7,7 @@ XLEN ?= 64 src_dir := . include $(src_dir)/rv64ui/Makefrag +include $(src_dir)/rv64uc/Makefrag include $(src_dir)/rv64um/Makefrag include $(src_dir)/rv64ua/Makefrag include $(src_dir)/rv64uf/Makefrag @@ -73,6 +74,7 @@ $(eval $(call compile_template,rv32si,-m32)) $(eval $(call compile_template,rv32mi,-m32)) ifeq ($(XLEN),64) $(eval $(call compile_template,rv64ui)) +$(eval $(call compile_template,rv64uc)) $(eval $(call compile_template,rv64um)) $(eval $(call compile_template,rv64ua)) $(eval $(call compile_template,rv64uf)) diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h index 4b1e1f5..721b80b 100644 --- a/isa/macros/scalar/test_macros.h +++ b/isa/macros/scalar/test_macros.h @@ -314,42 +314,6 @@ test_ ## testnum: \ li x5, 2; \ bne x4, x5, 1b \ -#----------------------------------------------------------------------- -# Test branch instructions -#----------------------------------------------------------------------- - -#define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x1, val1; \ - inst x1, 2f; \ - bne x0, TESTNUM, fail; \ -1: bne x0, TESTNUM, 3f; \ -2: inst x1, 1b; \ - bne x0, TESTNUM, fail; \ -3: - -#define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x1, val1; \ - inst x1, 1f; \ - bne x0, TESTNUM, 2f; \ -1: bne x0, TESTNUM, fail; \ -2: inst x1, 1b; \ -3: - -#define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: li x1, val1; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - inst x1, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - #define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \ test_ ## testnum: \ li TESTNUM, testnum; \ diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S index 77c9509..b975331 100644 --- a/isa/rv64mi/breakpoint.S +++ b/isa/rv64mi/breakpoint.S @@ -36,9 +36,10 @@ RVTEST_CODE_BEGIN csrr a1, tdrdata1 andi a1, a1, 0x7ff bne a0, a1, 2f + .align 2 1: # Trap handler should skip this instruction. - j fail + beqz x0, fail # Make sure reads don't trap. li TESTNUM, 3 diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S index c84242a..6e7be94 100644 --- a/isa/rv64mi/ma_addr.S +++ b/isa/rv64mi/ma_addr.S @@ -13,9 +13,9 @@ RVTEST_RV64M RVTEST_CODE_BEGIN - .align 3 .option norvc - auipc s0, 0 + + la s0, data # indicate it's a load test li s1, CAUSE_MISALIGNED_LOAD @@ -80,6 +80,9 @@ RVTEST_CODE_END .data RVTEST_DATA_BEGIN +data: + .dword 0 + TEST_DATA RVTEST_DATA_END diff --git a/isa/rv64uc/Makefrag b/isa/rv64uc/Makefrag new file mode 100644 index 0000000..f5e49b7 --- /dev/null +++ b/isa/rv64uc/Makefrag @@ -0,0 +1,11 @@ +#======================================================================= +# Makefrag for rv64uc tests +#----------------------------------------------------------------------- + +rv64uc_sc_tests = \ + rvc \ + +rv64uc_p_tests = $(addprefix rv64uc-p-, $(rv64uc_sc_tests)) +rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sc_tests)) + +spike_tests += $(rv64uc_p_tests) $(rv64uc_v_tests) diff --git a/isa/rv64uc/rvc.S b/isa/rv64uc/rvc.S new file mode 100644 index 0000000..4f2675a --- /dev/null +++ b/isa/rv64uc/rvc.S @@ -0,0 +1,151 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rvc.S +#----------------------------------------------------------------------------- +# +# Test RVC corner cases. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + .option push + .option norvc + + #define RVC_TEST_CASE(n, r, v, code...) \ + TEST_CASE (n, r, v, .option push; .option rvc; code; .option pop) + + // Make sure fetching a 4-byte instruction across a page boundary works. + li TESTNUM, 2 + li a1, 666 + li a2, 1 + RVC_TEST_CASE (2, a1, 2, \ + j 1f; \ + .align 12; \ + .skip 4094; \ + 1: addi a1, a2, 1) + + li sp, 0x1234 + RVC_TEST_CASE (3, a0, 0x1234 + 1020, c.addi4spn a0, sp, 1020) + RVC_TEST_CASE (4, sp, 0x1234 + 496, c.addi16sp sp, 496) + RVC_TEST_CASE (5, sp, 0x1234 + 496 - 512, c.addi16sp sp, -512) + + la a1, data + RVC_TEST_CASE (6, a2, 0xfffffffffedcba99, c.lw a0, 4(a1); addi a0, a0, 1; c.sw a0, 4(a1); c.lw a2, 4(a1)) +#ifdef __riscv64 + RVC_TEST_CASE (7, a2, 0xfedcba9976543211, c.ld a0, 0(a1); addi a0, a0, 1; c.sd a0, 0(a1); c.ld a2, 0(a1)) +#endif + + RVC_TEST_CASE (8, a0, -15, ori a0, x0, 1; c.addi a0, -16) + RVC_TEST_CASE (9, a5, -16, ori a5, x0, 1; c.li a5, -16) +#ifdef __riscv64 + RVC_TEST_CASE (10, a0, 0x76543210, ld a0, (a1); c.addiw a0, -1) +#endif + + RVC_TEST_CASE (11, s0, 0xffffffffffffffe1, c.lui s0, 0xfffe1; c.srai s0, 12) + RVC_TEST_CASE (12, s0, 0x000fffffffffffe1, c.lui s0, 0xfffe1; c.srli s0, 12) + RVC_TEST_CASE (13, s0, 0x000fffffffffffe1, c.lui s0, 0xfffe1; c.srli s0, 12) + RVC_TEST_CASE (14, s0, ~0x11, c.li s0, -2; c.andi s0, ~0x10) + RVC_TEST_CASE (15, s1, 14, li s1, 20; li a0, 6; c.sub s1, a0) + RVC_TEST_CASE (16, s1, 18, li s1, 20; li a0, 6; c.xor s1, a0) + RVC_TEST_CASE (17, s1, 22, li s1, 20; li a0, 6; c.or s1, a0) + RVC_TEST_CASE (18, s1, 4, li s1, 20; li a0, 6; c.and s1, a0) +#ifdef __riscv64 + RVC_TEST_CASE (19, s1, 0xffffffff80000000, li s1, 0x7fffffff; li a0, -1; c.subw s1, a0) + RVC_TEST_CASE (20, s1, 0xffffffff80000000, li s1, 0x7fffffff; li a0, 1; c.addw s1, a0) +#endif + RVC_TEST_CASE (21, s0, 0x12340, li s0, 0x1234; c.slli s0, 4) + + RVC_TEST_CASE (30, ra, 0, \ + li ra, 0; \ + c.j 1f; \ + c.j 2f; \ + 1:c.j 1f; \ + 2:j fail; \ + 1:) + + RVC_TEST_CASE (31, x0, 0, \ + li a0, 0; \ + c.beqz a0, 1f; \ + c.j 2f; \ + 1:c.j 1f; \ + 2:j fail; \ + 1:) + + RVC_TEST_CASE (32, x0, 0, \ + li a0, 1; \ + c.bnez a0, 1f; \ + c.j 2f; \ + 1:c.j 1f; \ + 2:j fail; \ + 1:) + + RVC_TEST_CASE (33, x0, 0, \ + li a0, 1; \ + c.beqz a0, 1f; \ + c.j 2f; \ + 1:c.j fail; \ + 2:) + + RVC_TEST_CASE (34, x0, 0, \ + li a0, 0; \ + c.bnez a0, 1f; \ + c.j 2f; \ + 1:c.j fail; \ + 2:) + + RVC_TEST_CASE (35, ra, 0, \ + la t0, 1f; \ + li ra, 0; \ + c.jr t0; \ + c.j 2f; \ + 1:c.j 1f; \ + 2:j fail; \ + 1:) + + RVC_TEST_CASE (36, ra, -2, \ + la t0, 1f; \ + li ra, 0; \ + c.jalr t0; \ + c.j 2f; \ + 1:c.j 1f; \ + 2:j fail; \ + 1:sub ra, ra, t0) + +#ifdef __riscv32 + RVC_TEST_CASE (37, ra, -2, \ + la t0, 1f; \ + li ra, 0; \ + c.jal 1f; \ + c.j 2f; \ + 1:c.j 1f; \ + 2:j fail; \ + 1:sub ra, ra, t0) +#endif + + la sp, data + RVC_TEST_CASE (40, a2, 0xfffffffffedcba99, c.lwsp a0, 12(sp); addi a0, a0, 1; c.swsp a0, 12(sp); c.lwsp a2, 12(sp)) +#ifdef __riscv64 + RVC_TEST_CASE (41, a2, 0xfedcba9976543211, c.ldsp a0, 8(sp); addi a0, a0, 1; c.sdsp a0, 8(sp); c.ldsp a2, 8(sp)) +#endif + + RVC_TEST_CASE (42, t0, 0x246, li a0, 0x123; c.mv t0, a0; c.add t0, a0) + + .option pop + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + +data: + .dword 0xfedcba9876543210 + .dword 0xfedcba9876543210 + +RVTEST_DATA_END -- 2.30.2