From 8508b484f13ccf05916fa684f5a1bc47ad6196ad Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 15 May 2023 20:16:15 +0100 Subject: [PATCH] fix empty slot in EXTRA move (swap) Mode[0] and Mode[1] in CROps, ff y/n is now Mode[1], VLI is now Mode[0]. https://bugs.libre-soc.org/show_bug.cgi?id=1083 --- src/openpower/consts.py | 2 +- src/openpower/decoder/power_enums.py | 1 - src/openpower/decoder/power_insn.py | 8 +++----- src/openpower/decoder/power_svp64_rm.py | 5 +---- 4 files changed, 5 insertions(+), 11 deletions(-) diff --git a/src/openpower/consts.py b/src/openpower/consts.py index 7dc9e4b2..9774eda3 100644 --- a/src/openpower/consts.py +++ b/src/openpower/consts.py @@ -263,7 +263,7 @@ class SVP64MODEb(_Const): INV = 2 # invert CR sense 0=set 1=unset CR_MSB = 3 # CR bit to update (with Rc=1) CR_LSB = 4 - VLI = 3 + VLI = 0 RC1 = 4 # update CR as if Rc=1 (when Rc=0) # LD immediate els (element-stride) locations, depending on mode ELS_NORMAL = 4 diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index 3bd7eee1..27f860b4 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -496,7 +496,6 @@ class SVP64RMMode(Enum): MAPREDUCE = 1 FFIRST = 2 SATURATE = 3 - PREDRES = 4 BRANCH = 5 diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index 44888ea2..ab1ead61 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -1262,8 +1262,6 @@ class ExtendableOperand(DynamicOperand): that_extra_reg = pairs.get(extra_reg, extra_reg) if this_extra_reg is that_extra_reg: bits = tuple(self.record.extra_idx(key=key, regtype=rtype)) - if len(bits) == 0: # empty slot, do not attempt to use it! - continue if this_extra_reg in found: assert found[this_extra_reg] == bits # check identical bits continue # skip - already found @@ -2587,7 +2585,7 @@ class SpecifierFF(SpecifierPredicate): if selector.mode.sel != 0: raise ValueError("cannot override mode") if self.record.svp64.mode is _SVMode.CROP: - selector.mode.sel = 0b10 + selector.mode.sel = 0b01 # HACK: please finally provide correct logic for CRs. if self.pred in (_SVP64Pred.RC1, _SVP64Pred.RC1_N): selector.mode[2] = (self.pred is _SVP64Pred.RC1_N) @@ -3315,8 +3313,8 @@ class RMSelector: table = ( (0b000000, 0b111000, "simple"), # simple (0b001000, 0b111000, "mr"), # mapreduce - (0b100001, 0b100001, "ff3"), # ffirst, 3-bit CR - (0b100000, 0b100000, "ff5"), # ffirst, 5-bit CR + (0b010001, 0b010001, "ff3"), # ffirst, 3-bit CR + (0b010000, 0b010000, "ff5"), # ffirst, 5-bit CR ) search = ((int(self.insn.prefix.rm.crop.mode) << 1) | int(self.record.svp64.extra_CR_3bit)) diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py index b88b9a38..cfc72c28 100644 --- a/src/openpower/decoder/power_svp64_rm.py +++ b/src/openpower/decoder/power_svp64_rm.py @@ -331,13 +331,10 @@ class SVP64RMModeDecode(Elaboratable): comb += self.mode.eq(SVP64RMMode.MAPREDUCE) with m.Else(): comb += self.mode.eq(SVP64RMMode.NORMAL) - with m.Case(1): + with m.Case(1,3): comb += self.mode.eq(SVP64RMMode.FFIRST) # ffirst with m.Case(2): comb += self.mode.eq(SVP64RMMode.SATURATE) # saturate - with m.Case(3): - # mode = 0b11: arithmetic predicate-result - comb += self.mode.eq(SVP64RMMode.PREDRES) # pred result # extract "reverse gear" for mapreduce mode with m.If((~is_ldst) & # not for LD/ST -- 2.30.2