From 850b311d04a834645e5704b6d8a848a1b8902f62 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 7 Jun 2019 18:36:46 +0200 Subject: [PATCH] cpu/vexriscv: update submodule --- litex/soc/cores/cpu/vexriscv/verilog | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog index c6dfccaa..4b5a515d 160000 --- a/litex/soc/cores/cpu/vexriscv/verilog +++ b/litex/soc/cores/cpu/vexriscv/verilog @@ -1 +1 @@ -Subproject commit c6dfccaaa3c830b8c9c5037bbd4e1a8d43ca5bf0 +Subproject commit 4b5a515d4bbb22df0eb44a6e53cc76b3da1ff470 -- 2.30.2