From 850e8d3d56d9418d5e170a3dd9ddb68bcf01a984 Mon Sep 17 00:00:00 2001 From: Dorit Naishlos Date: Mon, 27 Sep 2004 20:23:38 +0000 Subject: [PATCH] rs6000.c (rs6000_legitimate_address, [...]): Handle AND pattern * config/rs6000/rs6000.c (rs6000_legitimate_address, print_operand): Handle AND pattern From-SVN: r88196 --- gcc/ChangeLog | 5 +++++ gcc/config/rs6000/rs6000.c | 14 ++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8c0e62927b3..29d7774b9aa 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2004-09-27 Dorit Naishlos + + * config/rs6000/rs6000.c (rs6000_legitimate_address, print_operand): + Handle AND pattern + 2004-09-27 Joseph S. Myers PR c/13804 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 39ace238fa3..602498bd9da 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3189,6 +3189,7 @@ legitimate_indexed_address_p (rtx x, int strict) if (GET_CODE (x) != PLUS) return false; + op0 = XEXP (x, 0); op1 = XEXP (x, 1); @@ -3805,6 +3806,14 @@ rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, int rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict) { + /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */ + if (TARGET_ALTIVEC + && ALTIVEC_VECTOR_MODE (mode) + && GET_CODE (x) == AND + && GET_CODE (XEXP (x, 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) == -16) + x = XEXP (x, 0); + if (RS6000_SYMBOL_REF_TLS_P (x)) return 0; if (legitimate_indirect_address_p (x, reg_ok_strict)) @@ -10559,6 +10568,11 @@ print_operand (FILE *file, rtx x, int code) /* Fall through. Must be [reg+reg]. */ } + if (TARGET_ALTIVEC + && GET_CODE (tmp) == AND + && GET_CODE (XEXP (tmp, 1)) == CONST_INT + && INTVAL (XEXP (tmp, 1)) == -16) + tmp = XEXP (tmp, 0); if (GET_CODE (tmp) == REG) fprintf (file, "0,%s", reg_names[REGNO (tmp)]); else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG) -- 2.30.2