From 851d055f60243396075499e8681a8218111c7ead Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 18 Sep 2022 15:04:22 +0100 Subject: [PATCH] reduce NORMAL svp64 mode down to a mask-value search --- src/openpower/decoder/power_insn.py | 37 +++++++++++++---------------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index c39ec2d8..f1744728 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -1746,28 +1746,23 @@ class RM(BaseRM): rm = self if record.svp64.mode is _SVMode.NORMAL: + # concatenate mode 5-bit with Rc (LSB) then do a mask/map search + # mode Rc mask Rc action(getattr) + table = [(0b000000, 0b111000, "simple"), # simple (no Rc) + (0b001000, 0b111000, "smr"), # mapreduce (no Rc) + (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0 + (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1 + (0b100000, 0b110000, "sat"), # saturation(no Rc) + (0b110000, 0b110001, "prrc0"), # predicate, Rc=0 + (0b110001, 0b110001, "prrc1"), # predicate, Rc=1 + ] + rm = rm.normal - if rm.mode[0:2] == 0b00: - if rm.mode[2] == 0b0: - rm = rm.simple - else: - rm = rm.smr - elif rm.mode[0:2] == 0b01: - if Rc: - rm = rm.ffrc1 - else: - rm = rm.ffrc0 - elif rm.mode[0:2] == 0b10: - if self.subvl == 0b00: - rm = rm.sat - else: - if rm.mode[4]: - rm = rm.satx - elif rm.mode[0:2] == 0b11: - if Rc: - rm = rm.prrc1 - else: - rm = rm.prrc0 + search = (int(rm.mode) << 1) | Rc + for (val, mask, action) in table: + if (val&search) == (mask&search): + rm = getattr(rm, action) + break elif record.svp64.mode is _SVMode.LDST_IMM: rm = rm.ldst_imm -- 2.30.2