From 852a13111dba712f147ea76b8924eda12d053644 Mon Sep 17 00:00:00 2001 From: Steven Bosscher Date: Wed, 30 Jun 2004 09:32:41 +0000 Subject: [PATCH] * config/c4x/c4x.md: Fix comment. From-SVN: r83898 --- gcc/ChangeLog | 8 ++++++-- gcc/config/c4x/c4x.md | 18 ++---------------- 2 files changed, 8 insertions(+), 18 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b6334b78684..bf7e9080a29 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,8 @@ -2004-0630 Akos Kiss +2004-06-30 Steven Bosscher + + * config/c4x/c4x.md: Fix comment. + +2004-06-30 Akos Kiss * arm.md (cond_return_inverted): Add "length" attribute. @@ -4861,7 +4865,7 @@ 2004-05-22 Zack Weinberg - * tree.h (struct tree_decl): Add possibly_inlined bit. + * tree.h (struct tree_decl): Add possibly_inlined bit. (DECL_POSSIBLY_INLINED): New accessor macro. * cgraph.h: Remove declaration of cgraph_inline_hash. * cgraph.c: Remove definition of cgraph_inline_hash. diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md index 3c2d2f86e9a..adfdbac9d06 100644 --- a/gcc/config/c4x/c4x.md +++ b/gcc/config/c4x/c4x.md @@ -474,31 +474,17 @@ ]) ; -; C4x FUNCTIONAL UNITS -; -; Define functional units for instruction scheduling to minimize -; pipeline conflicts. +; C4x PIPELINE MODEL ; ; With the C3x, an external memory write (with no wait states) takes ; two cycles and an external memory read (with no wait states) takes ; one cycle. However, an external read following an external write ; takes two cycles. With internal memory, reads and writes take ; half a cycle. -; ; When a C4x address register is loaded it will not be available for ; an extra machine cycle. Calculating with a C4x address register -; makes it unavailable for 2 machine cycles. To notify GCC of these -; pipeline delays, each of the auxiliary and index registers are declared -; as separate functional units. +; makes it unavailable for 2 machine cycles. ; -; (define_function_unit NAME MULTIPLICITY SIMULTANEITY -; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) -; -; MULTIPLICITY 1 (C4x has no independent identical function units) -; SIMULTANEITY 0 (C4x is pipelined) -; READY_DELAY 1 (Results usually ready after every cyle) -; ISSUE_DELAY 1 (Can issue insns every cycle) - ; Just some dummy definitions. The real work is done in c4x_adjust_cost. ; These are needed so the min/max READY_DELAY is known. -- 2.30.2