From 853825e53772ceec030b985ee40b4edb15333fda Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 16 Oct 2022 12:01:10 +0100
Subject: [PATCH] rewrite get_idx_out in ISACaller to split out RT/out
 relationship

---
 src/openpower/decoder/isa/caller.py | 49 +++++++++++++++--------------
 1 file changed, 25 insertions(+), 24 deletions(-)

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index bb373703..c1a0979b 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -533,46 +533,47 @@ def get_cr_out(dec2, name):
 
 
 # TODO, really should just be using PowerDecoder2
-def get_idx_out(dec2, name, ewmode=False):
+def get_out_map(dec2, name):
     op = dec2.dec.op
     out_sel = yield op.out_sel
     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
     out = yield dec2.e.write_reg.data
-    o_isvec = yield dec2.o_isvec
-    if ewmode:
-        offs = yield dec2.e.write_reg.offs
-        base = yield dec2.e.write_reg.base
-        out = (out, base, offs)
     # identify which regnames map to out / o2
-    if name == 'BF':
-        log("get_idx_out", out_sel, out, o_isvec)
     if name == 'RA':
-        log("get_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
         if out_sel == OutSel.RA.value:
-            return out, o_isvec
+            return True
     elif name == 'RT':
-        log("get_idx_out", out_sel, OutSel.RT.value,
-            OutSel.RT_OR_ZERO.value, out, o_isvec,
-            dec2.dec.RT)
         if out_sel == OutSel.RT.value:
-            return out, o_isvec
+            return True
         if out_sel == OutSel.RT_OR_ZERO.value and out != 0:
-            return out, o_isvec
+            return True
     elif name == 'RT_OR_ZERO':
-        log("get_idx_out", out_sel, OutSel.RT.value,
-            OutSel.RT_OR_ZERO.value, out, o_isvec,
-            dec2.dec.RT)
         if out_sel == OutSel.RT_OR_ZERO.value:
-            return out, o_isvec
+            return True
     elif name == 'FRA':
-        log("get_idx_out", out_sel, OutSel.FRA.value, out, o_isvec)
         if out_sel == OutSel.FRA.value:
-            return out, o_isvec
+            return True
     elif name == 'FRT':
-        log("get_idx_out", out_sel, OutSel.FRT.value,
-            OutSel.FRT.value, out, o_isvec)
         if out_sel == OutSel.FRT.value:
-            return out, o_isvec
+            return True
+    return False
+
+
+# TODO, really should just be using PowerDecoder2
+def get_idx_out(dec2, name, ewmode=False):
+    op = dec2.dec.op
+    out_sel = yield op.out_sel
+    # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
+    out = yield dec2.e.write_reg.data
+    o_isvec = yield dec2.o_isvec
+    if ewmode:
+        offs = yield dec2.e.write_reg.offs
+        base = yield dec2.e.write_reg.base
+        out = (out, base, offs)
+    # identify which regnames map to out / o2
+    if get_out_map(dec2, name):
+        log("get_idx_out", name, out_sel, out, o_isvec)
+        return out, o_isvec
     log("get_idx_out not found", name, out_sel, out, o_isvec)
     return None, False
 
-- 
2.30.2