From 85438c977d27ca6fc104da8fcd12a42c1d9a3684 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 26 Mar 2023 14:57:32 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls008.mdwn | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/openpower/sv/rfc/ls008.mdwn b/openpower/sv/rfc/ls008.mdwn index e5d46ef0a..81bb66aac 100644 --- a/openpower/sv/rfc/ls008.mdwn +++ b/openpower/sv/rfc/ls008.mdwn @@ -71,11 +71,8 @@ Power ISA is synonymous with Supercomputing and the early Supercomputers (ETA-10, ILLIAC-IV, CDC200, Cray) had Vectorisation. It is therefore anomalous -that Power ISA does not have Scalable Vectors, instead having the legacy -"PackedSIMD" paradigm. Fortunately this presents -the opportunity to modernise Power ISA learning from both past ISA features and -mistakes placing it far above the top of Supercomputing for the next two decades -and beyond. +that Power ISA does not have Scalable Vectors. This presents the opportunity to +modernise Power ISA keeping it at the top of Supercomputing. **Notes and Observations**: @@ -89,9 +86,7 @@ and beyond. operations to a runtime-selectable choice of 128-bit, 256-bit, 512-bit or 1024-bit. 3. Massive reductions in instruction count of between 2x and 20x have been demonstrated with SVP64, which is far beyond anything ever achieved by any *general-purpose* - ISA Extension added to any ISA in the history of Computing. Normal reductions - expected are of the order of 5 to 10% being considered a highly worthwhile exercise - to pursue inclusion. + ISA Extension added to any ISA in the history of Computing. **Changes** -- 2.30.2