From 85898351d9a01fb34425dc97fcaf041070bc7cdf Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Sun, 6 Nov 2022 12:29:55 +0300 Subject: [PATCH] power_insn: rename register operand class --- src/openpower/decoder/power_insn.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index fd772024..4e12ccd1 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -639,7 +639,7 @@ class NonZeroOperand(DynamicOperand): yield str(int(value) + 1) -class RegisterOperand(DynamicOperand): +class ExtendableOperand(DynamicOperand): def sv_spec_enter(self, value, span): return (value, span) @@ -741,7 +741,7 @@ class RegisterOperand(DynamicOperand): yield f"{vector}{prefix}{int(value)}" -class GPROperand(RegisterOperand): +class GPROperand(ExtendableOperand): def assemble(self, value, insn, record): if isinstance(value, str): value = value.lower() @@ -758,7 +758,7 @@ class GPROperand(RegisterOperand): verbosity=verbosity, indent=indent) -class FPROperand(RegisterOperand): +class FPROperand(ExtendableOperand): def assemble(self, value, insn, record): if isinstance(value, str): value = value.lower() @@ -775,11 +775,11 @@ class FPROperand(RegisterOperand): verbosity=verbosity, indent=indent) -class CR3Operand(RegisterOperand): +class CR3Operand(ExtendableOperand): pass -class CR5Operand(RegisterOperand): +class CR5Operand(ExtendableOperand): def sv_spec_enter(self, value, span): value = _SelectableInt(value=(value.value >> 2), bits=3) return (value, span) -- 2.30.2