From 85970bb28b1b3ba1b0d82641d281be5566de687d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 18 Jul 2020 15:03:31 +0100 Subject: [PATCH] whoops use slice not range --- src/soc/fu/trap/main_stage.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index 5eeddd5b..39f4326d 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -212,7 +212,7 @@ class TrapMainStage(PipeModBase): # don't understand but it's in the spec. again: bits 32-34 # are copied from srr1_i and need *restoring* to msr_i - bits = range(63-31,63-29+1) # bits 29, 30, 31 (Power notation) + bits = slice(63-31,63-29+1) # bits 29, 30, 31 (Power notation) with m.If((msr_i[bits] == Const(0b010, 3)) & (srr1_i[bits] == Const(0b000, 3))): comb += msr_o.data[bits].eq(msr_i[bits]) -- 2.30.2