From 859936f2118f87d1b1ddec0f762a1a3b72a23ad9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 7 Jul 2021 16:31:08 +0100 Subject: [PATCH] ffmuls test, had to add to b not a in expected results --- src/openpower/decoder/isa/test_caller_svp64_fft.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py index 3001050b..181de643 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_fft.py +++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py @@ -185,7 +185,7 @@ class DecoderTestCase(FHDLTestCase): fprs[i+6] = fp64toselectable(b) fprs[i+10] = fp64toselectable(c) mul = a * c - t = a + mul + t = b + mul u = b - mul t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single u = DOUBLE2SINGLE(fp64toselectable(u)) # from double -- 2.30.2