From 85a059bf773f9224bdd7106dbc5c8639d20d3af2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 25 Apr 2020 12:11:10 +0200 Subject: [PATCH] bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal. We need to provide enough information to ease support and understand the issue. The write leveling/read leveling are doing there best to calibrate the DRAM correctly and memtest gives the final result. --- litex/soc/software/bios/sdram.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c index eca275d9..ff4e8f40 100644 --- a/litex/soc/software/bios/sdram.c +++ b/litex/soc/software/bios/sdram.c @@ -442,7 +442,7 @@ static void write_level_cdly_range(unsigned int *best_error, int *best_cdly, delay_mean /= SDRAM_PHY_MODULES; /* we want it to be at the start */ - int ideal_delay = 1; + int ideal_delay = 4*SDRAM_PHY_DELAYS/32; int error = ideal_delay - delay_mean; if (error < 0) error *= -1; @@ -1069,13 +1069,11 @@ int sdrlevel(void) #ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE printf("Write leveling:\n"); if (_write_level_cdly_scan) { - if(!write_level()) - return 0; + write_level(); } else { /* use only the current cdly */ int delays[SDRAM_PHY_MODULES]; - if (!write_level_scan(delays, 1)) - return 0; + write_level_scan(delays, 1); } #endif -- 2.30.2