From 85a14895ca31ec8c34bf5c296a5740a798b06693 Mon Sep 17 00:00:00 2001 From: Dan Ravensloft Date: Tue, 10 Dec 2019 13:40:32 +0000 Subject: [PATCH] synth_intel: a10gx -> arria10gx --- techlibs/intel/Makefile.inc | 2 +- techlibs/intel/{a10gx => arria10gx}/cells_arith.v | 0 techlibs/intel/{a10gx => arria10gx}/cells_map.v | 0 techlibs/intel/{a10gx => arria10gx}/cells_sim.v | 0 techlibs/intel/synth_intel.cc | 6 +++--- 5 files changed, 4 insertions(+), 4 deletions(-) rename techlibs/intel/{a10gx => arria10gx}/cells_arith.v (100%) rename techlibs/intel/{a10gx => arria10gx}/cells_map.v (100%) rename techlibs/intel/{a10gx => arria10gx}/cells_sim.v (100%) diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index 92a83b5af..d97a9b58f 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -7,7 +7,7 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k. $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v)) # Add the cell models and mappings for the VQM backend -families := max10 a10gx cyclonev cyclone10lp cycloneiv cycloneive +families := max10 arria10gx cyclonev cyclone10lp cycloneiv cycloneive $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v))) $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v))) #$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v)) diff --git a/techlibs/intel/a10gx/cells_arith.v b/techlibs/intel/arria10gx/cells_arith.v similarity index 100% rename from techlibs/intel/a10gx/cells_arith.v rename to techlibs/intel/arria10gx/cells_arith.v diff --git a/techlibs/intel/a10gx/cells_map.v b/techlibs/intel/arria10gx/cells_map.v similarity index 100% rename from techlibs/intel/a10gx/cells_map.v rename to techlibs/intel/arria10gx/cells_map.v diff --git a/techlibs/intel/a10gx/cells_sim.v b/techlibs/intel/arria10gx/cells_sim.v similarity index 100% rename from techlibs/intel/a10gx/cells_sim.v rename to techlibs/intel/arria10gx/cells_sim.v diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 5e6d2df2c..c8c690e45 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -36,7 +36,7 @@ struct SynthIntelPass : public ScriptPass { log("\n"); log("This command runs synthesis for Intel FPGAs.\n"); log("\n"); - log(" -family \n"); + log(" -family \n"); log(" generate the synthesis netlist for the specified family.\n"); log(" MAX10 is the default target if no family argument specified.\n"); log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n"); @@ -148,7 +148,7 @@ struct SynthIntelPass : public ScriptPass { if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); if (family_opt != "max10" && - family_opt != "a10gx" && + family_opt != "arria10gx" && family_opt != "cyclonev" && family_opt != "cycloneiv" && family_opt != "cycloneive" && @@ -214,7 +214,7 @@ struct SynthIntelPass : public ScriptPass { } if (check_label("map_luts")) { - if (family_opt == "a10gx" || family_opt == "cyclonev") + if (family_opt == "arria10gx" || family_opt == "cyclonev") run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); else run("abc -lut 4" + string(retime ? " -dff" : "")); -- 2.30.2