From 85b16025d35561e81cca633b6fbf6cbf0b10f333 Mon Sep 17 00:00:00 2001
From: whitequark <cz@m-labs.hk>
Date: Thu, 13 Dec 2018 04:51:15 +0000
Subject: [PATCH] back.verilog: detect undriven public wires using Yosys.

This should never happen, and is certainly a logic bug in nMigen.
---
 nmigen/back/verilog.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/nmigen/back/verilog.py b/nmigen/back/verilog.py
index 90a5c2f..8ac5f1f 100644
--- a/nmigen/back/verilog.py
+++ b/nmigen/back/verilog.py
@@ -19,6 +19,7 @@ def convert(*args, **kwargs):
         stderr=subprocess.PIPE,
         encoding="utf-8")
     verilog_text, error = popen.communicate("""
+# Convert nMigen's RTLIL to readable Verilog.
 read_ilang <<rtlil
 {}
 rtlil
@@ -27,6 +28,9 @@ proc_arst
 proc_dff
 proc_clean
 write_verilog
+# Make sure there are no undriven wires in generated RTLIL.
+proc
+select -assert-none w:* i:* %a %d c:* %co* %a %d n:$* %d
 """.format(il_text))
     if popen.returncode:
         raise YosysError(error.strip())
-- 
2.30.2