From 85c09b0518630f580b3cdc82728b22ad09b1ca64 Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Thu, 24 Oct 1996 20:49:06 +0000 Subject: [PATCH] * simops.c (OP_500): Fix displacement handling for sld.w. (OP_501): Similarly for sst.w. More fixes exposed by tda testing. --- sim/v850/ChangeLog | 3 +++ sim/v850/simops.c | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog index 00e90a3e299..1325b2aefc8 100644 --- a/sim/v850/ChangeLog +++ b/sim/v850/ChangeLog @@ -1,5 +1,8 @@ Thu Oct 24 12:26:35 1996 Jeffrey A Law (law@cygnus.com) + * simops.c (OP_500): Fix displacement handling for sld.w. + (OP_501): Similarly for sst.w. + * simops.c (trace_input): Remove all references to SEXT7. (OP_300, OP_400, OP_500, OP_380, OP_480, OP_501): Displacement is zero extended for sst/sld instructions. diff --git a/sim/v850/simops.c b/sim/v850/simops.c index b26680ee4bc..77102328f1d 100644 --- a/sim/v850/simops.c +++ b/sim/v850/simops.c @@ -456,7 +456,7 @@ OP_500 () trace_input ("sld.w", OP_LOAD16, 4); temp = OP[1]; temp &= 0x7f; - op2 = temp << 2; + op2 = temp << 1; result = load_mem (State.regs[30] + op2, 4); State.regs[OP[0]] = result; trace_output (OP_LOAD16); @@ -505,7 +505,7 @@ OP_501 () op0 = State.regs[OP[0]]; temp = OP[1]; temp &= 0x7f; - op1 = temp << 2; + op1 = temp << 1; store_mem (State.regs[30] + op1, 4, op0); trace_output (OP_STORE16); } -- 2.30.2