From 85c1d093b7a0faea31628485d5213b44d73ffee7 Mon Sep 17 00:00:00 2001
From: MANIKANDAN <MANIKANDAN@web>
Date: Mon, 27 Sep 2021 06:59:10 +0100
Subject: [PATCH]

---
 about_us.mdwn | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/about_us.mdwn b/about_us.mdwn
index c74ced180..fbd1d24bd 100644
--- a/about_us.mdwn
+++ b/about_us.mdwn
@@ -218,7 +218,7 @@ Alain's website: <http://phcomp.co.uk>
 
 ## [[Manikandan Nagarajan|Manik]]
 
-* Languages: Verilog HDL, C, Python & TCL
+* Languages: Verilog HDL, VHDL, C, Python & TCL
 * Experience : Domain Specific Architecture Design and Implementation, IP Core Development, System on Chip, FPGA System Design, Chip Tapeout, Crypto Chip Design, Authentication Protocol Design. 
 * LinkedIn Profile: [[https://www.linkedin.com/in/manikandan-nagarajan-2156171a0/]]
 * Availability: 8~10hrs/week
-- 
2.30.2