From 85de15beadd41148334092daed8f1e2fe6226ef4 Mon Sep 17 00:00:00 2001
From: Michael Nolan <mtnolan2640@gmail.com>
Date: Fri, 8 May 2020 11:56:09 -0400
Subject: [PATCH] Add FPPipeContext to alu pipe_data

---
 src/soc/alu/formal/proof_input_stage.py |  2 +-
 src/soc/alu/pipe_data.py                | 37 +++++++++++++++++++------
 2 files changed, 29 insertions(+), 10 deletions(-)

diff --git a/src/soc/alu/formal/proof_input_stage.py b/src/soc/alu/formal/proof_input_stage.py
index 22cd52bf..b11ec4f3 100644
--- a/src/soc/alu/formal/proof_input_stage.py
+++ b/src/soc/alu/formal/proof_input_stage.py
@@ -23,7 +23,7 @@ class Driver(Elaboratable):
         m = Module()
         comb = m.d.comb
 
-        pspec = ALUPipeSpec()
+        pspec = ALUPipeSpec(id_wid=2, op_wid=1)
         m.submodules.dut = dut = ALUInputStage(pspec)
 
         a = Signal(64)
diff --git a/src/soc/alu/pipe_data.py b/src/soc/alu/pipe_data.py
index e2231c85..cd79abaf 100644
--- a/src/soc/alu/pipe_data.py
+++ b/src/soc/alu/pipe_data.py
@@ -1,27 +1,46 @@
 from nmigen import Signal, Const
 from nmutil.dynamicpipe import SimpleHandshakeRedir
 from soc.alu.alu_input_record import CompALUOpSubset
+from ieee754.fpcommon.getop import FPPipeContext
 
 
-class ALUInitialData:
+class IntegerData:
 
     def __init__(self, pspec):
         self.op = CompALUOpSubset()
-        self.a = Signal(64, reset_less=True)
-        self.b = Signal(64, reset_less=True)
+        self.ctx = FPPipeContext(pspec)
+        self.muxid = self.ctx.muxid
 
     def __iter__(self):
         yield from self.op
-        yield self.a
-        yield self.b
+        yield from self.ctx
 
     def eq(self, i):
-        return [self.op.eq(i.op),
-                self.a.eq(i.a), self.b.eq(i.b)]
+        return [self.op.eq(i.op), self.ctx.eq(i.ctx)]
 
 
+class ALUInitialData(IntegerData):
+    def __init__(self, pspec):
+        super().__init__(pspec)
+        self.a = Signal(64, reset_less=True)
+        self.b = Signal(64, reset_less=True)
 
+    def __iter__(self):
+        yield from super().__iter__()
+        yield self.a
+        yield self.b
 
-class ALUPipeSpec:
-    def __init__(self):
+    def eq(self, i):
+        lst = super().eq(i)
+        return lst + [self.a.eq(i.a), self.b.eq(i.b)]
+
+class IntPipeSpec:
+    def __init__(self, id_wid=2, op_wid=1):
+        self.id_wid = id_wid
+        self.op_wid = op_wid
+        self.opkls = CompALUOpSubset
+
+class ALUPipeSpec(IntPipeSpec):
+    def __init__(self, id_wid, op_wid):
+        super().__init__(id_wid, op_wid)
         self.pipekls = SimpleHandshakeRedir
-- 
2.30.2