From 8615012c05130f592b4ef6b11ac6af7cc28718d2 Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Tue, 26 Sep 2017 17:37:14 +0000 Subject: [PATCH] rs6000.md (extendsi2): Add a splitter to do sign extension from a vector register to a GPR by doing a... 2017-09-26 Michael Meissner * config/rs6000/rs6000.md (extendsi2): Add a splitter to do sign extension from a vector register to a GPR by doing a 32-bit direct move and then an EXTSW. (extendsi2 splitter): Likewise. From-SVN: r253208 --- gcc/ChangeLog | 7 +++++++ gcc/config/rs6000/rs6000.md | 24 ++++++++++++++++++++---- 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b2a2755dcf4..195571333be 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-09-26 Michael Meissner + + * config/rs6000/rs6000.md (extendsi2): Add a splitter to do + sign extension from a vector register to a GPR by doing a 32-bit + direct move and then an EXTSW. + (extendsi2 splitter): Likewise. + 2017-09-26 Martin Jambor * tree-sra.c (compare_access_positions): Put integral types first, diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9019ba8ae98..f22dbce494a 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -986,8 +986,11 @@ (define_insn "extendsi2" - [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wl,wu,wj,wK,wH") - (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" "Y,r,Z,Z,r,wK,wH")))] + [(set (match_operand:EXTSI 0 "gpc_reg_operand" + "=r, r, wl, wu, wj, wK, wH, wr") + + (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" + "Y, r, Z, Z, r, wK, wH, ?wIwH")))] "" "@ lwa%U1%X1 %0,%1 @@ -996,10 +999,23 @@ lxsiwax %x0,%y1 mtvsrwa %x0,%1 vextsw2d %0,%1 + # #" - [(set_attr "type" "load,exts,fpload,fpload,mffgpr,vecexts,vecperm") + [(set_attr "type" "load,exts,fpload,fpload,mffgpr,vecexts,vecperm,mftgpr") (set_attr "sign_extend" "yes") - (set_attr "length" "4,4,4,4,4,4,8")]) + (set_attr "length" "4,4,4,4,4,4,8,8")]) + +(define_split + [(set (match_operand:EXTSI 0 "int_reg_operand") + (sign_extend:EXTSI (match_operand:SI 1 "vsx_register_operand")))] + "TARGET_DIRECT_MOVE_64BIT && reload_completed" + [(set (match_dup 2) + (match_dup 1)) + (set (match_dup 0) + (sign_extend:DI (match_dup 2)))] +{ + operands[2] = gen_rtx_REG (SImode, reg_or_subregno (operands[0])); +}) (define_split [(set (match_operand:DI 0 "altivec_register_operand") -- 2.30.2