From 861d3c9d78613e45721d146d78d67fd5076df511 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Fri, 21 Jul 2023 17:33:38 -0700 Subject: [PATCH] add cfuged --- openpower/isa/fixedlogical.mdwn | 24 ++++++++++++++++++++- openpower/isatables/RM-1P-2S1D.csv | 1 + openpower/isatables/minor_31.csv | 1 + src/openpower/decoder/isa/caller.py | 2 +- src/openpower/decoder/power_enums.py | 2 ++ src/openpower/test/logical/logical_cases.py | 24 +++++++++++++++++++++ 6 files changed, 52 insertions(+), 2 deletions(-) diff --git a/openpower/isa/fixedlogical.mdwn b/openpower/isa/fixedlogical.mdwn index 43aafe51..b2bba382 100644 --- a/openpower/isa/fixedlogical.mdwn +++ b/openpower/isa/fixedlogical.mdwn @@ -512,4 +512,26 @@ Special Registers Altered: None - +# Centrifuge Doubleword + +X-Form + +* cfuged RA,RS,RB + +Pseudo-code: + + ptr0 <- 0 + ptr1 <- 0 + result[0:63] <- 0 + do i = 0 to 63 + if (RB)[i] = 0 then + result[ptr0] <- (RS)[i] + ptr0 <- ptr0 + 1 + if (RB)[63-i] = 1 then + result[63-ptr1] <- (RS)[63-i] + ptr1 <- ptr1 + 1 + RA <- result + +Special Registers Altered: + + None diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv index c96a038a..75ee3ac1 100644 --- a/openpower/isatables/RM-1P-2S1D.csv +++ b/openpower/isatables/RM-1P-2S1D.csv @@ -17,6 +17,7 @@ cmpeqb,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0 bmask,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0 cntlzdm,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RS,RB,0,RA,0,0,0 addex,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0 +cfuged,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RS,RB,0,RA,0,0,0 bpermd,NORMAL,,1P,EXTRA3,NO,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0 modud,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0 moduw,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0 diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv index b10dbf76..b77193ab 100644 --- a/openpower/isatables/minor_31.csv +++ b/openpower/isatables/minor_31.csv @@ -20,6 +20,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 0b0010111011,LOGICAL,OP_BYTEREV,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,brd,X,,0, 0b0100111010,ALU,OP_CBCDTD,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,cbcdtd,X,,, 0b0100011010,ALU,OP_CDTBCD,RS,NONE,NONE,RA,NONE,NONE,1,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,cdtbcd,X,,, +0b0011011100,LOGICAL,OP_CFUGE,RS,RB,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,cfuged,X,,0, 0b0011111100,LOGICAL,OP_BPERM,RS,RB,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,bpermd,X,,, 0b0000000000,ALU,OP_CMP,RA,RB,NONE,NONE,NONE,BF,1,0,ONE,0,NONE,0,0,0,0,0,1,NONE,0,0,cmp,X,,, 0b0111111100,LOGICAL,OP_CMPB,RS,RB,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,cmpb,X,,, diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index b79295cc..4e12c4d4 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1969,7 +1969,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): "ctfpr", "ctfprs", "mtfpr", "mtfprs", "maddsubrs", "maddrs", "msubrs", - "cntlzdm", "cnttzdm", + "cfuged", "cntlzdm", "cnttzdm", ]: illegal = False ins_name = dotstrp diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index 1b37bf3e..54959a29 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -741,6 +741,7 @@ _insns = [ "bpermd", "cbcdtd", "cdtbcd", + "cfuged", "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb", "cntlzd", "cntlzdm", "cntlzw", "cnttzd", "cnttzdm", "cnttzw", "cprop", # AV bitmanip @@ -957,6 +958,7 @@ class MicrOp(Enum): OP_MADDRS = 105 OP_MSUBRS = 106 OP_BYTEREV = 107 + OP_CFUGE = 108 class SelType(Enum): diff --git a/src/openpower/test/logical/logical_cases.py b/src/openpower/test/logical/logical_cases.py index 6e5709d0..809096e6 100644 --- a/src/openpower/test/logical/logical_cases.py +++ b/src/openpower/test/logical/logical_cases.py @@ -127,6 +127,30 @@ class LogicalTestCase(TestAccumulatorBase): initial_regs[2] = random.randint(0, (1 << 64)-1) self.add_case(Program(lst, bigendian), initial_regs) + def case_cfuged(self): + prog = Program(list(SVP64Asm(["cfuged 3,4,5"])), bigendian) + for case_idx in range(200): + gprs = [0] * 32 + gprs[4] = hash_256(f"cfuged {case_idx} r4") % 2**64 + gprs[5] = hash_256(f"cfuged {case_idx} r5") % 2**64 + e = ExpectedState(pc=4, int_regs=gprs) + zeros = [] + ones = [] + for i in range(64): + bit = 1 << i + if gprs[5] & bit: + ones.append(bool(gprs[4] & bit)) + else: + zeros.append(bool(gprs[4] & bit)) + bits = ones + zeros + e.intregs[3] = 0 + for i, v in enumerate(bits): + e.intregs[3] |= v << i + with self.subTest( + case_idx=case_idx, RS_in=hex(gprs[4]), + RB_in=hex(gprs[5]), expected_RA=hex(e.intregs[3])): + self.add_case(prog, gprs, expected=e) + def case_cntlzdm(self): prog = Program(list(SVP64Asm(["cntlzdm 3,4,5"])), bigendian) for case_idx in range(200): -- 2.30.2