From 8630342fb28d8d5fde51d6a11498126f68c1c864 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 24 Sep 2022 17:08:59 +0100 Subject: [PATCH] set sv_mode to 0b01 in element-strided --- src/openpower/sv/trans/svp64.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index cf26f43f..596514cd 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -1030,6 +1030,7 @@ class SVP64Asm: # identify if the op is a LD/ST. # see https://libre-soc.org/openpower/sv/ldst/ is_ldst = rm['mode'] in [ 'LDST_IDX', 'LDST_IMM'] + is_ldst_idx = rm['mode'] == 'LDST_IDX' is_ld = v30b_op.startswith("l") and is_ldst is_st = v30b_op.startswith("s") and is_ldst @@ -1101,6 +1102,9 @@ class SVP64Asm: # element-strided LD/ST elif encmode == 'els': ldst_elstride = 1 + # in indexed mode, set sv_mode=0b01 + if is_ldst_idx: + sv_mode = 0b01 # saturation elif encmode == 'sats': assert sv_mode is None -- 2.30.2