From 864824c8d498e3261f55491fd8d19673e06a4317 Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 16 Dec 2018 10:38:25 +0000 Subject: [PATCH] compat.fhdl: reexport Array. --- doc/COMPAT_SUMMARY.md | 4 ++-- nmigen/compat/fhdl/structure.py | 7 ++----- nmigen/hdl/ast.py | 2 +- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/doc/COMPAT_SUMMARY.md b/doc/COMPAT_SUMMARY.md index c09eb63..c218086 100644 --- a/doc/COMPAT_SUMMARY.md +++ b/doc/COMPAT_SUMMARY.md @@ -77,8 +77,8 @@ Compatibility summary - (-) `_check_statement` **obs** → `Statement.wrap` - (+) `If` **obs** → `.hdl.dsl.Module.If` - (+) `Case` **obs** → `.hdl.dsl.Module.Switch` - - (−) `_ArrayProxy` ? - - (−) `Array` ? + - (+) `_ArrayProxy` → `.hdl.ast.ArrayProxy`, `choices=`→`elems=`, `key=`→`index=` + - (+) `Array` id - (+) `ClockDomain` → `.hdl.cd.ClockDomain` - (−) `_ClockDomainList` ? - (−) `SPECIAL_INPUT`/`SPECIAL_OUTPUT`/`SPECIAL_INOUT` ? diff --git a/nmigen/compat/fhdl/structure.py b/nmigen/compat/fhdl/structure.py index 95c68c2..1743df2 100644 --- a/nmigen/compat/fhdl/structure.py +++ b/nmigen/compat/fhdl/structure.py @@ -2,7 +2,8 @@ from collections import OrderedDict from ...tools import deprecated from ...hdl import ast -from ...hdl.ast import DUID, Value, Signal, Mux, Cat, Repl, Const, C, ClockSignal, ResetSignal +from ...hdl.ast import (DUID, Value, Signal, Mux, Cat, Repl, Const, C, ClockSignal, ResetSignal, + Array, ArrayProxy as _ArrayProxy) from ...hdl.cd import ClockDomain @@ -84,8 +85,4 @@ class Case(ast.Switch): return self -def Array(*args): - raise NotImplementedError - - (SPECIAL_INPUT, SPECIAL_OUTPUT, SPECIAL_INOUT) = range(3) diff --git a/nmigen/hdl/ast.py b/nmigen/hdl/ast.py index 8ccd552..a2d3adf 100644 --- a/nmigen/hdl/ast.py +++ b/nmigen/hdl/ast.py @@ -713,7 +713,7 @@ class Array(MutableSequence): master.dat_r.eq(buses[sel].dat_r), ] """ - def __init__(self, iterable): + def __init__(self, iterable=()): self._inner = list(iterable) self._proxy_at = None self._mutable = True -- 2.30.2