From 866c1bc31063e3b776a2230814ae0ff95e038550 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 17 Jul 2018 06:49:03 +0100 Subject: [PATCH] add pwm test Makefile --- src/bsv/bsv_lib/ClockDiv.bsv | 44 +++++++++++++++++++++ src/bsv/bsv_lib/Makefile.pwm.templates | 53 ++++++++++++++++++++++++++ src/bsv/bsv_lib/instance_defines.bsv | 2 + 3 files changed, 99 insertions(+) create mode 100644 src/bsv/bsv_lib/ClockDiv.bsv create mode 100644 src/bsv/bsv_lib/Makefile.pwm.templates diff --git a/src/bsv/bsv_lib/ClockDiv.bsv b/src/bsv/bsv_lib/ClockDiv.bsv new file mode 100644 index 0000000..b84894d --- /dev/null +++ b/src/bsv/bsv_lib/ClockDiv.bsv @@ -0,0 +1,44 @@ +package ClockDiv; + /*=== Project imports ==*/ + import Clocks::*; + /*======================*/ + // =========================== Clock divider module ================ // + interface Ifc_ClockDiv#(numeric type width); + interface Clock slowclock; + method Action divisor(Bit#(width) in); + endinterface + + module mkClockDiv(Ifc_ClockDiv#(width)); + let defclock <- exposeCurrentClock; + Reg#(Bit#(1)) clk <- mkReg(0); + Reg#(Bit#(width)) rg_divisor <- mkReg(0); + Reg#(Bit#(width)) rg_counter <- mkReg(0); + MakeClockIfc#(Bit#(1)) new_clock <- mkUngatedClock(0); + MuxClkIfc clock_selector <- mkUngatedClockMux(new_clock.new_clk,defclock); + Bool clockmux_sel = rg_divisor!=0; + rule increment_counter; + if(rg_divisor!=0 && rg_counter >= rg_divisor)begin + rg_counter <= 0; + clk <= ~ clk; + end + else + rg_counter <= rg_counter + 1; + endrule + + rule generate_clock; + new_clock.setClockValue(clk); + endrule + + rule select_clock; + clock_selector.select(clockmux_sel); + endrule + + method Action divisor(Bit#(width) in); + rg_divisor <= in != 0 ? in - 1 : 0; + endmethod + + interface slowclock=clock_selector.clock_out; + endmodule + // ============================================================== // + +endpackage diff --git a/src/bsv/bsv_lib/Makefile.pwm.templates b/src/bsv/bsv_lib/Makefile.pwm.templates new file mode 100644 index 0000000..8794355 --- /dev/null +++ b/src/bsv/bsv_lib/Makefile.pwm.templates @@ -0,0 +1,53 @@ +### Makefile for the srio + +TOP_MODULE:=mkPWM_bus +TOP_FILE:=pwm.bsv +HOMEDIR:=./ +TOP_DIR:=./ +BSVBUILDDIR:=./build/ +VERILOGDIR:=./verilog/ +BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC +FPGA=xc7a100tcsg324-1 +export HOMEDIR=./ +export TOP=$(TOP_MODULE) + +default: full_clean compile link simulate + +timing_area: full_clean generate_verilog vivado_build + +.PHONY: compile +compile: + @echo Compiling $(TOP_MODULE).... + @mkdir -p $(BSVBUILDDIR) + @bsc -u -sim -simdir $(BSVBUILDDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) -keep-fires -p $(BSVINCDIR) -D NAME=neel -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) + @echo Compilation finished + +.PHONY: link +link: + @echo Linking $(TOP_MODULE)... + @mkdir -p bin + @bsc -e $(TOP_MODULE) -sim -o ./bin/out -simdir $(BSVBUILDDIR) -p .:%/Prelude:%/Libraries:%/Libraries/BlueNoC:./c_files -keep-fires -bdir $(BSVBUILDDIR) -keep-fires ./c_files/checker.c + @echo Linking finished + +.PHONY: generate_verilog +generate_verilog: + @echo Compiling $(TOP_MODULE) in verilog ... + @mkdir -p $(BSVBUILDDIR); + @mkdir -p $(VERILOGDIR); + @bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR)\ + $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout\ + -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) || (echo "BSC COMPILE ERROR"; exit 1) + +.PHONY: simulate +simulate: + @echo Simulation... + ./bin/out + @echo Simulation finished. + +.PHONY: clean +clean: + rm -rf build bin *.jou *.log + +.PHONY: full_clean +full_clean: clean + rm -rf verilog fpga diff --git a/src/bsv/bsv_lib/instance_defines.bsv b/src/bsv/bsv_lib/instance_defines.bsv index 8dbed4a..3df5b1e 100644 --- a/src/bsv/bsv_lib/instance_defines.bsv +++ b/src/bsv/bsv_lib/instance_defines.bsv @@ -3,3 +3,5 @@ `define USERSPACE 0 `define PADDR 32 `define Reg_width 32 +`define PWM_AXI4Lite enable + -- 2.30.2