From 8677fd4ee0f0bad4977261b11643a543020e6752 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 20 May 2020 19:45:12 +0100 Subject: [PATCH] store CR lut result in temporary --- src/soc/fu/cr/main_stage.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py index 00417651..2ec877e5 100644 --- a/src/soc/fu/cr/main_stage.py +++ b/src/soc/fu/cr/main_stage.py @@ -108,8 +108,10 @@ class CRMainStage(PipeModBase): # Use the two input bits to look up the result in the LUT idx = Signal(2, reset_less=True) + lv = Signal(1, reset_less=True) comb += idx.eq(Cat(cr_arr[bb], cr_arr[ba])) - comb += cr_out_arr[bt].eq(lut[idx]) + comb += lv.eq(lut[idx]) + comb += cr_out_arr[bt].eq(lv) ##### mtcrf ##### with m.Case(InternalOp.OP_MTCRF): -- 2.30.2