From 86843876773f9b39c5665150c8881674c2f5b883 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 23 Aug 2019 11:38:46 +0100 Subject: [PATCH] use bit_select instead of part, again --- src/ieee754/part_mul_add/multiply.py | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py index c4773d3f..3366a4f9 100644 --- a/src/ieee754/part_mul_add/multiply.py +++ b/src/ieee754/part_mul_add/multiply.py @@ -726,8 +726,8 @@ class ProductTerm(Elaboratable): bsb = Signal(self.width, reset_less=True) a_index, b_index = self.a_index, self.b_index pwidth = self.pwidth - m.d.comb += bsa.eq(self.a.part(a_index * pwidth, pwidth)) - m.d.comb += bsb.eq(self.b.part(b_index * pwidth, pwidth)) + m.d.comb += bsa.eq(self.a.bit_select(a_index * pwidth, pwidth)) + m.d.comb += bsb.eq(self.b.bit_select(b_index * pwidth, pwidth)) m.d.comb += self.ti.eq(bsa * bsb) m.d.comb += self.term.eq(get_term(self.ti, self.shift, self.enabled)) """ @@ -741,8 +741,8 @@ class ProductTerm(Elaboratable): asel = Signal(width, reset_less=True) bsel = Signal(width, reset_less=True) a_index, b_index = self.a_index, self.b_index - m.d.comb += asel.eq(self.a.part(a_index * pwidth, pwidth)) - m.d.comb += bsel.eq(self.b.part(b_index * pwidth, pwidth)) + m.d.comb += asel.eq(self.a.bit_select(a_index * pwidth, pwidth)) + m.d.comb += bsel.eq(self.b.bit_select(b_index * pwidth, pwidth)) m.d.comb += bsa.eq(get_term(asel, self.shift, self.enabled)) m.d.comb += bsb.eq(get_term(bsel, self.shift, self.enabled)) m.d.comb += self.ti.eq(bsa * bsb) @@ -922,7 +922,7 @@ class Part(Elaboratable): pa = LSBNegTerm(bit_wid) setattr(m.submodules, "lnt_%d_a_%d" % (bit_wid, i), pa) m.d.comb += pa.part.eq(parts[i]) - m.d.comb += pa.op.eq(self.a.part(bit_wid * i, bit_wid)) + m.d.comb += pa.op.eq(self.a.bit_select(bit_wid * i, bit_wid)) m.d.comb += pa.signed.eq(self.b_signed[i * byte_width]) # yes b m.d.comb += pa.msb.eq(self.b[(i + 1) * bit_wid - 1]) # really, b nat.append(pa.nt) @@ -932,7 +932,7 @@ class Part(Elaboratable): pb = LSBNegTerm(bit_wid) setattr(m.submodules, "lnt_%d_b_%d" % (bit_wid, i), pb) m.d.comb += pb.part.eq(parts[i]) - m.d.comb += pb.op.eq(self.b.part(bit_wid * i, bit_wid)) + m.d.comb += pb.op.eq(self.b.bit_select(bit_wid * i, bit_wid)) m.d.comb += pb.signed.eq(self.a_signed[i * byte_width]) # yes a m.d.comb += pb.msb.eq(self.a[(i + 1) * bit_wid - 1]) # really, a nbt.append(pb.nt) @@ -970,8 +970,8 @@ class IntermediateOut(Elaboratable): op = Signal(w, reset_less=True, name="op%d_%d" % (w, i)) m.d.comb += op.eq( Mux(self.part_ops[sel * i] == OP_MUL_LOW, - self.intermed.part(i * w*2, w), - self.intermed.part(i * w*2 + w, w))) + self.intermed.bit_select(i * w*2, w), + self.intermed.bit_select(i * w*2 + w, w))) ol.append(op) m.d.comb += self.output.eq(Cat(*ol)) @@ -1040,8 +1040,10 @@ class FinalOut(Elaboratable): op = Signal(8, reset_less=True, name="op_%d" % i) m.d.comb += op.eq( Mux(d8[i] | d16[i // 2], - Mux(d8[i], i8.part(i * 8, 8), i16.part(i * 8, 8)), - Mux(d32[i // 4], i32.part(i * 8, 8), i64.part(i * 8, 8)))) + Mux(d8[i], i8.bit_select(i * 8, 8), + i16.bit_select(i * 8, 8)), + Mux(d32[i // 4], i32.bit_select(i * 8, 8), + i64.bit_select(i * 8, 8)))) ol.append(op) m.d.comb += self.out.eq(Cat(*ol)) m.d.comb += self.intermediate_output.eq(self.i.intermediate_output) -- 2.30.2