From 86a5fbfd4afb4fb53ab8ea0a13dda33b32f8b79b Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 26 Nov 2019 18:29:00 +0100 Subject: [PATCH] radv: fix enabling sample shading with SampleID/SamplePosition When a fragment shader includes an input variable decorated with SampleId or SamplePosition, sample shading should be enabled because minSampleShadingFactor is expected to be 1.0. Cc: 19.2, 19.3 Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_pipeline.c | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index dc2cbc4884b..95b1684fdf8 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1099,15 +1099,32 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, int ps_iter_samples = 1; uint32_t mask = 0xffff; - if (vkms) + if (vkms) { ms->num_samples = vkms->rasterizationSamples; - else - ms->num_samples = 1; - if (vkms) - ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms); - if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) { - ps_iter_samples = ms->num_samples; + /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading: + * + * "Sample shading is enabled for a graphics pipeline: + * + * - If the interface of the fragment shader entry point of the + * graphics pipeline includes an input variable decorated + * with SampleId or SamplePosition. In this case + * minSampleShadingFactor takes the value 1.0. + * - Else if the sampleShadingEnable member of the + * VkPipelineMultisampleStateCreateInfo structure specified + * when creating the graphics pipeline is set to VK_TRUE. In + * this case minSampleShadingFactor takes the value of + * VkPipelineMultisampleStateCreateInfo::minSampleShading. + * + * Otherwise, sample shading is considered disabled." + */ + if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) { + ps_iter_samples = ms->num_samples; + } else { + ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms); + } + } else { + ms->num_samples = 1; } const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order = -- 2.30.2