From 86ce43999eaed10c3b9d141bb2f66bf98ad45eb6 Mon Sep 17 00:00:00 2001 From: Sylvain Munaut Date: Sat, 24 Nov 2018 18:49:23 +0100 Subject: [PATCH] Make return value of $clog2 signed As per Verilog 2005 - 17.11.1. Fixes #708 Signed-off-by: Sylvain Munaut --- frontends/ast/simplify.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index bb4c9735d..55abe165f 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1913,7 +1913,7 @@ skip_dynamic_range_lvalue_expansion:; if (arg_value.bits.at(i) == RTLIL::State::S1) result = i + 1; - newNode = mkconst_int(result, false); + newNode = mkconst_int(result, true); goto apply_newNode; } -- 2.30.2