From 86d17003c42f930004b8ecfd1c0befacf9de348b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 30 Jun 2022 19:53:09 +0100 Subject: [PATCH] blech correct text-matching when non-space after bracket --- openpower/pandoc_img.py | 70 ++++++++++++++++++++++------------------- 1 file changed, 37 insertions(+), 33 deletions(-) diff --git a/openpower/pandoc_img.py b/openpower/pandoc_img.py index 2569d0a52..458b11f45 100755 --- a/openpower/pandoc_img.py +++ b/openpower/pandoc_img.py @@ -46,39 +46,43 @@ def inlinenotes(k, v, f, meta): return Image(*v) if k == 'Str' and f == 'latex': # link page - if v.startswith("[[") and v.endswith("]]"): - link = v[2:-2] - out.write(" link %s\n" % link) - lookups = {'sv': 'Scalable Vectors for Power ISA', - 'SV|sv': 'Scalable Vectors for Power ISA', - 'sv/overview': 'Overview Chapter', - 'sv/compliancy_levels': 'Compliancy Levels', - 'sv/svp64': 'SVP64 Chapter', - 'sv/sprs': 'SPRs', - 'sv/normal': 'Arithmetic Mode', - 'sv/ldst': 'Load/Store Mode', - 'sv/cr_ops': 'Condition Register Fields Mode', - 'sv/branches': 'Branch Mode', - 'sv/setvl': 'setvl instruction', - 'sv/svstep': 'svstep instruction', - 'sv/remap': 'REMAP subsystem', - 'sv/mv.swizzle': 'Swizzle Move', - 'sv/mv.vec': 'Pack / Unpack', - 'svp64/appendix': 'SVP64 Appendix', - 'sv/svp64_quirks': 'SVP64 Quirks', - 'openpower/isa/simplev': 'Simple-V pseudocode', - 'sv/opcode_regs_deduped': 'SVP64 Augmentation Table', - } - if link in lookups: - out.write(" found %s\n" % lookups[link]) - return Link(['', [], []], - [Str(lookups[link])], - ['#%s' % link, '']) - if '|' in link: - link, ref = link.split("|") - return Link(['', [], []], - [Str(link)], - [ref, '']) + if not v.startswith("[["): + return + find_brack = v.find(']]') + if find_brack == -1: + return + link = v[2:find_brack-2] + out.write(" link %s\n" % link) + lookups = {'sv': 'Scalable Vectors for Power ISA', + 'SV|sv': 'Scalable Vectors for Power ISA', + 'sv/overview': 'Overview Chapter', + 'sv/compliancy_levels': 'Compliancy Levels', + 'sv/svp64': 'SVP64 Chapter', + 'sv/sprs': 'SPRs', + 'sv/normal': 'Arithmetic Mode', + 'sv/ldst': 'Load/Store Mode', + 'sv/cr_ops': 'Condition Register Fields Mode', + 'sv/branches': 'Branch Mode', + 'sv/setvl': 'setvl instruction', + 'sv/svstep': 'svstep instruction', + 'sv/remap': 'REMAP subsystem', + 'sv/mv.swizzle': 'Swizzle Move', + 'sv/mv.vec': 'Pack / Unpack', + 'svp64/appendix': 'SVP64 Appendix', + 'sv/svp64_quirks': 'SVP64 Quirks', + 'openpower/isa/simplev': 'Simple-V pseudocode', + 'sv/opcode_regs_deduped': 'SVP64 Augmentation Table', + } + if link in lookups: + out.write(" found %s\n" % lookups[link]) + return [Link(['', [], []], + [Str(lookups[link])], + ['#%s' % link, '']), Str(v[find_brack:])] + if '|' in link: + link, ref = link.split("|") + return [Link(['', [], []], + [Str(link)], + [ref, '']), Str(v[find_brack:])] if k == 'Link': out.write(" link type %s\n" % \ (type(v[1][0]))) -- 2.30.2