From 87042ef15585c7b0482dede64a2ad1418c1e3441 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 25 Sep 2021 13:49:52 +0100 Subject: [PATCH 1/1] code-comments and dummy functions --- src/soc/simple/test/test_runner.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index b16a68f3..31c6b7b4 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -325,6 +325,8 @@ class TestRunner(FHDLTestCase): intclk = ClockSignal("coresync") comb += intclk.eq(ClockSignal()) + # TODO these should probably move into HDLRunner's constructor + # and become HDLRunner.pc_i and HDLRunner.svstate_i if self.run_hdl: pc_i = Signal(32) @@ -343,6 +345,9 @@ class TestRunner(FHDLTestCase): ###### PREPARATION PHASE AT START OF RUNNING ####### # StateRunner.setup_during_test() + if self.run_sim: + simrun.setup_during_test() # TODO, some arguments? + if self.run_hdl: # start in stopped yield from set_dmi(hdlrun.dmi, DBGCore.CTRL, 1<