From 870738bcf71053f9533087ce67a1a7c2742b4b6d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 3 Apr 2022 11:30:44 +0100 Subject: [PATCH] add alternative pc_reset argument to issuer_verilog.py which propagates right the way down to core.py next to msr_reset it is now possible to set the pc_reset value. these actually have to go into the regfile as initial values, which will be fun for an ASIC --- Makefile | 6 ++++++ src/soc/simple/core.py | 5 ++++- src/soc/simple/issuer_verilog.py | 15 +++++++++++++-- 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index e89ad1d9..f318ae31 100644 --- a/Makefile +++ b/Makefile @@ -63,6 +63,12 @@ microwatt_external_core: python3 src/soc/simple/issuer_verilog.py --microwatt-compat --enable-mmu \ external_core_top.v +microwatt_external_core_spi: + python3 src/soc/simple/issuer_verilog.py --microwatt-compat \ + --enable-mmu \ + --pc-reset 0x10000000 \ + external_core_top.v + # build the litex libresoc SoC without 4k SRAMs ls180_verilog_build: ls180_verilog make -C soc/soc/litex/florent ls180 diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 0479508a..20a396c3 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -161,9 +161,12 @@ class NonProductionCore(ControlBase): # alternative reset values for STATE regs self.msr_at_reset = 0x0 + self.pc_at_reset = 0x0 if hasattr(pspec, "msr_reset") and isinstance(pspec.msr_reset, int): self.msr_at_reset = pspec.msr_reset - state_resets = [0x0, # PC at reset + if hasattr(pspec, "pc_reset") and isinstance(pspec.pc_reset, int): + self.pc_at_reset = pspec.pc_reset + state_resets = [self.pc_at_reset, # PC at reset self.msr_at_reset, # MSR at reset 0x0, # SVSTATE at reset 0x0, # DEC at reset diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py index 4198ae26..1ddc4211 100644 --- a/src/soc/simple/issuer_verilog.py +++ b/src/soc/simple/issuer_verilog.py @@ -59,6 +59,8 @@ if __name__ == '__main__': parser.add_argument("--disable-svp64", dest='svp64', action="store_false", help="disable SVP64", default=False) + parser.add_argument("--pc-reset", default=0, + help="Set PC at reset (default 0)") parser.add_argument("--xlen", default=64, type=int, help="Set register width [default 64]") # create a module that's directly compatible as a drop-in replacement @@ -106,9 +108,15 @@ if __name__ == '__main__': ldst_ifacetype = 'bare_wb' imem_ifacetype = 'bare_wb' - # default MSR (TODO, provide option to set default PC as well) + # default MSR msr_reset = (1<