From 87145ef0afd7d88ece9093ecc82f2c13e8b6bdab Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 14 Oct 2018 06:28:16 +0100 Subject: [PATCH] rv_add in store --- riscv/insns/sb.h | 2 +- riscv/insns/sd.h | 2 +- riscv/insns/sw.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h index 8729c2d..ad656cf 100644 --- a/riscv/insns/sb.h +++ b/riscv/insns/sb.h @@ -1 +1 @@ -MMU.store_uint8(RS1 + insn.s_imm(), RS2); +MMU.store_uint8(rv_add(RS1, insn.s_imm()), RS2); diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h index 664deb2..df56fbe 100644 --- a/riscv/insns/sd.h +++ b/riscv/insns/sd.h @@ -1,2 +1,2 @@ require_rv64; -MMU.store_uint64(RS1 + insn.s_imm(), RS2); +MMU.store_uint64(rv_add(RS1, insn.s_imm()), RS2); diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h index aa5ead3..32c2851 100644 --- a/riscv/insns/sw.h +++ b/riscv/insns/sw.h @@ -1 +1 @@ -MMU.store_uint32(RS1 + insn.s_imm(), RS2); +MMU.store_uint32(rv_add(RS1, insn.s_imm()), RS2); -- 2.30.2