From 871903e83a215ebd45c8890dcf5d7145e21558d4 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Fri, 10 Jul 2020 15:06:51 +0200 Subject: [PATCH] Rename VCD file output --- gram/test/test_soc.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py index b7aa5ca..4d243b8 100644 --- a/gram/test/test_soc.py +++ b/gram/test/test_soc.py @@ -156,7 +156,7 @@ class SocTestCase(FHDLTestCase): yield self.assertEqual(res, 0xACAB2020) - runSimulation(m, process, "test_soc.vcd") + runSimulation(m, process, "test_soc_multiple_reads.vcd") def test_interleaved_read_write(self): m = Module() @@ -177,4 +177,4 @@ class SocTestCase(FHDLTestCase): res = yield from wb_read(soc.bus, 0x10000004 >> 2, 0xF, 128) self.assertEqual(res, 0x12345678) - runSimulation(m, process, "test_soc.vcd") + runSimulation(m, process, "test_soc_interleaved_read_write.vcd") -- 2.30.2