From 871b958f85bd473a9102214a41a4569cf6d682c7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 21 Jan 2019 10:39:34 +0100 Subject: [PATCH] boards/targets: improve presentation --- litex/boards/targets/arty.py | 6 ++- litex/boards/targets/de0nano.py | 66 +++++++++++++++------------- litex/boards/targets/genesys2.py | 6 ++- litex/boards/targets/kc705.py | 6 ++- litex/boards/targets/kcu105.py | 5 ++- litex/boards/targets/minispartan6.py | 5 ++- litex/boards/targets/nexys4ddr.py | 6 ++- litex/boards/targets/nexys_video.py | 6 ++- litex/boards/targets/simple.py | 4 ++ litex/boards/targets/ulx3s.py | 6 ++- litex/boards/targets/versa_ecp5.py | 6 ++- 11 files changed, 82 insertions(+), 40 deletions(-) diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 98d45c65..115df401 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -17,6 +17,7 @@ from litedram.phy import s7ddrphy from liteeth.phy.mii import LiteEthPHYMII from liteeth.core.mac import LiteEthMAC +# CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform, sys_clk_freq): @@ -41,6 +42,7 @@ class _CRG(Module): Instance("BUFG", i_I=eth_clk, o_O=platform.request("eth_ref_clk")), ] +# BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): csr_map = { @@ -64,6 +66,7 @@ class BaseSoC(SoCSDRAM): sdram_module.geom_settings, sdram_module.timing_settings) +# EthernetSoC -------------------------------------------------------------------------------------- class EthernetSoC(BaseSoC): csr_map = { @@ -103,9 +106,10 @@ class EthernetSoC(BaseSoC): self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) +# Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC port to Arty") + parser = argparse.ArgumentParser(description="LiteX SoC on Arty") builder_args(parser) soc_sdram_args(parser) parser.add_argument("--with-ethernet", action="store_true", diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py index e46c5757..70b4a5c9 100755 --- a/litex/boards/targets/de0nano.py +++ b/litex/boards/targets/de0nano.py @@ -12,6 +12,7 @@ from litex.soc.integration.builder import * from litedram.modules import IS42S16160 from litedram.phy import GENSDRPHY +# CRG ---------------------------------------------------------------------------------------------- class _ALTPLL(Module): def __init__(self, period_in, name, phase_shift, operation_mode): @@ -20,36 +21,36 @@ class _ALTPLL(Module): self.specials += \ Instance("ALTPLL", - p_bandwidth_type = "AUTO", - p_clk0_divide_by = 1, - p_clk0_duty_cycle = 50, - p_clk0_multiply_by = 2, - p_clk0_phase_shift = "{}".format(str(phase_shift)), - p_compensate_clock = "CLK0", - p_inclk0_input_frequency = int(period_in*1000), - p_intended_device_family = "Cyclone IV E", - p_lpm_hint = "CBX_MODULE_PREFIX={}_pll".format(name), - p_lpm_type = "altpll", - p_operation_mode = operation_mode, - i_inclk=self.clk_in, - o_clk=self.clk_out, - i_areset=0, - i_clkena=0x3f, - i_clkswitch=0, - i_configupdate=0, - i_extclkena=0xf, - i_fbin=1, - i_pfdena=1, - i_phasecounterselect=0xf, - i_phasestep=1, - i_phaseupdown=1, - i_pllena=1, - i_scanaclr=0, - i_scanclk=0, - i_scanclkena=1, - i_scandata=0, - i_scanread=0, - i_scanwrite=0 + p_bandwidth_type="AUTO", + p_clk0_divide_by=1, + p_clk0_duty_cycle=50, + p_clk0_multiply_by=2, + p_clk0_phase_shift="{}".format(str(phase_shift)), + p_compensate_clock="CLK0", + p_inclk0_input_frequency=int(period_in*1000), + p_intended_device_family="Cyclone IV E", + p_lpm_hint="CBX_MODULE_PREFIX={}_pll".format(name), + p_lpm_type="altpll", + p_operation_mode=operation_mode, + i_inclk=self.clk_in, + o_clk=self.clk_out, + i_areset=0, + i_clkena=0x3f, + i_clkswitch=0, + i_configupdate=0, + i_extclkena=0xf, + i_fbin=1, + i_pfdena=1, + i_phasecounterselect=0xf, + i_phasestep=1, + i_phaseupdown=1, + i_pllena=1, + i_scanaclr=0, + i_scanclk=0, + i_scanclkena=1, + i_scandata=0, + i_scanread=0, + i_scanwrite=0 ) @@ -86,6 +87,7 @@ class _CRG(Module): self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) +# BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): def __init__(self, **kwargs): @@ -104,8 +106,10 @@ class BaseSoC(SoCSDRAM): sdram_module.geom_settings, sdram_module.timing_settings) +# Build -------------------------------------------------------------------------------------------- + def main(): - parser = argparse.ArgumentParser(description="LiteX SoC port to the Altera DE0 Nano") + parser = argparse.ArgumentParser(description="LiteX SoC on DE0 Nano") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 663eaf0b..afe3992b 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -17,6 +17,7 @@ from litedram.phy import s7ddrphy from liteeth.phy.s7rgmii import LiteEthPHYRGMII from liteeth.core.mac import LiteEthMAC +# CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform, sys_clk_freq): @@ -33,6 +34,7 @@ class _CRG(Module): self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) +# BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): csr_map = { @@ -56,6 +58,7 @@ class BaseSoC(SoCSDRAM): sdram_module.geom_settings, sdram_module.timing_settings) +# EthernetSoC ------------------------------------------------------------------------------------------ class EthernetSoC(BaseSoC): csr_map = { @@ -95,9 +98,10 @@ class EthernetSoC(BaseSoC): self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) +# Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC port to Genesys 2") + parser = argparse.ArgumentParser(description="LiteX SoC on Genesys2") builder_args(parser) soc_sdram_args(parser) parser.add_argument("--with-ethernet", action="store_true", diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index c2f94e5a..dc5d4e22 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -17,6 +17,7 @@ from litedram.phy import s7ddrphy from liteeth.phy import LiteEthPHY from liteeth.core.mac import LiteEthMAC +# CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform, sys_clk_freq): @@ -33,6 +34,7 @@ class _CRG(Module): self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) +# BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): csr_map = { @@ -56,6 +58,7 @@ class BaseSoC(SoCSDRAM): sdram_module.geom_settings, sdram_module.timing_settings) +# EthernetSoC ------------------------------------------------------------------------------------------ class EthernetSoC(BaseSoC): csr_map = { @@ -95,9 +98,10 @@ class EthernetSoC(BaseSoC): self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) +# Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC port to KC705") + parser = argparse.ArgumentParser(description="LiteX SoC on KC705") builder_args(parser) soc_sdram_args(parser) parser.add_argument("--with-ethernet", action="store_true", diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index d4c04fa6..f496e53e 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -14,6 +14,7 @@ from litex.soc.integration.builder import * from litedram.modules import EDY4016A from litedram.phy import usddrphy +# CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform, sys_clk_freq): @@ -66,6 +67,7 @@ class _CRG(Module): AsyncResetSynchronizer(self.cd_ic, ic_reset) ] +# BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): csr_map = { @@ -90,9 +92,10 @@ class BaseSoC(SoCSDRAM): sdram_module.geom_settings, sdram_module.timing_settings) +# Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC port to KCU105") + parser = argparse.ArgumentParser(description="LiteX SoC on KCU105") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py index 44744073..00cc506c 100755 --- a/litex/boards/targets/minispartan6.py +++ b/litex/boards/targets/minispartan6.py @@ -14,6 +14,7 @@ from litex.soc.integration.builder import * from litedram.modules import AS4C16M16 from litedram.phy import GENSDRPHY +# CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform, clk_freq): @@ -65,6 +66,7 @@ class _CRG(Module): i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk, o_Q=platform.request("sdram_clock")) +# BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): def __init__(self, **kwargs): @@ -83,9 +85,10 @@ class BaseSoC(SoCSDRAM): sdram_module.geom_settings, sdram_module.timing_settings) +# Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC port to the MiniSpartan6") + parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index 72c5e896..e1209828 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -14,6 +14,8 @@ from litex.soc.integration.builder import * from litedram.modules import MT47H64M16 from litedram.phy import s7ddrphy +# CRG ---------------------------------------------------------------------------------------------- + class _CRG(Module): def __init__(self, platform, sys_clk_freq): @@ -34,6 +36,7 @@ class _CRG(Module): self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) +# BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): csr_map = { @@ -58,9 +61,10 @@ class BaseSoC(SoCSDRAM): sdram_module.timing_settings) self.add_constant("MEMTEST_ADDR_SIZE", 0) # FIXME +# Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC port to Nexys4DDR") + parser = argparse.ArgumentParser(description="LiteX SoC on Nexys4DDR") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index ca485774..902d2ec5 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -17,6 +17,7 @@ from litedram.phy import s7ddrphy from liteeth.phy.s7rgmii import LiteEthPHYRGMII from liteeth.core.mac import LiteEthMAC +# CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform, sys_clk_freq): @@ -37,6 +38,7 @@ class _CRG(Module): self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) +# BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): csr_map = { @@ -60,6 +62,7 @@ class BaseSoC(SoCSDRAM): sdram_module.geom_settings, sdram_module.timing_settings) +# EthernetSoC -------------------------------------------------------------------------------------- class EthernetSoC(BaseSoC): csr_map = { @@ -99,9 +102,10 @@ class EthernetSoC(BaseSoC): self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) +# Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC port to Nexys Video") + parser = argparse.ArgumentParser(description="LiteX SoC on Nexys Video") builder_args(parser) soc_sdram_args(parser) parser.add_argument("--with-ethernet", action="store_true", diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index 68f98293..3c5f02c9 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -12,6 +12,8 @@ from litex.soc.integration.builder import * from liteeth.phy import LiteEthPHY from liteeth.core.mac import LiteEthMAC +# BaseSoC ------------------------------------------------------------------------------------------ + class BaseSoC(SoCCore): def __init__(self, platform, **kwargs): sys_clk_freq = int(1e9/platform.default_clk_period) @@ -21,6 +23,7 @@ class BaseSoC(SoCCore): **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) +# EthernetSoC -------------------------------------------------------------------------------------- class EthernetSoC(BaseSoC): csr_map = { @@ -49,6 +52,7 @@ class EthernetSoC(BaseSoC): self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) +# Build -------------------------------------------------------------------------------------------- def main(): parser = argparse.ArgumentParser(description="Generic LiteX SoC") diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index 76a4c067..00b452ca 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -14,6 +14,7 @@ from litex.soc.integration.builder import * from litedram.modules import MT48LC16M16 from litedram.phy import GENSDRPHY +# CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform): @@ -45,6 +46,7 @@ class _CRG(Module): wifi_gpio0 = platform.request("wifi_gpio0") self.comb += wifi_gpio0.eq(1) +# BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): def __init__(self, **kwargs): @@ -63,8 +65,10 @@ class BaseSoC(SoCSDRAM): sdram_module.geom_settings, sdram_module.timing_settings) +# Build -------------------------------------------------------------------------------------------- + def main(): - parser = argparse.ArgumentParser(description="LiteX SoC port to the ULX3S") + parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index 921d9002..8a551d49 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -14,6 +14,7 @@ from litex.soc.integration.builder import * from litedram.modules import AS4C32M16 from litedram.phy import GENSDRPHY +# CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform): @@ -41,6 +42,7 @@ class _CRG(Module): # sdram clock self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) +# BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): def __init__(self, **kwargs): @@ -60,8 +62,10 @@ class BaseSoC(SoCSDRAM): sdram_module.geom_settings, sdram_module.timing_settings) +# Build -------------------------------------------------------------------------------------------- + def main(): - parser = argparse.ArgumentParser(description="LiteX SoC port to the Versa ECP5") + parser = argparse.ArgumentParser(description="LiteX SoC on ECP5") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() -- 2.30.2