From 8728f11676d6de23fc691dcea0d54e5654879fa8 Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 7 Sep 2021 15:43:38 +0100 Subject: [PATCH] --- openpower/sv/cr_ops.mdwn | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn index 5e49d7ab0..f6e48d89a 100644 --- a/openpower/sv/cr_ops.mdwn +++ b/openpower/sv/cr_ops.mdwn @@ -20,6 +20,13 @@ SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations: | - | - | ----- | --- |---------|----------------- | |dz |VLi| 01 | inv | CR-bit | normal mode | |sz |VLi| 01 | inv | dz Rc1 | VLSET mode | +| / | / | 00 | 0 | dz sz | normal mode | +| / | / | 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 | +| / | / | 00 | 1 | 1 CRM | parallel reduce mode (mapreduce), SUBVL=1 | +| / | / | 00 | 1 | SVM RG | subvector reduce mode, SUBVL>1 | +| / | / | 10 | / | / / | RESERVED | +|dz | / | 11 | inv | CR-bit | Rc=1: pred-result CR sel | +|sz | / | 11 | inv | dz RC1 | Rc=0: pred-result z/nonz | Fields: -- 2.30.2