From 872d8d49e98fc5a4090ce20d902afbd0090c8c84 Mon Sep 17 00:00:00 2001
From: Jim Paris <jim@jtan.com>
Date: Thu, 17 May 2018 00:06:49 -0400
Subject: [PATCH] Skip spaces around macro arguments

---
 frontends/verilog/preproc.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index c43ff4e3a..00124cb42 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -244,6 +244,7 @@ static bool try_expand_macro(std::set<std::string> &defines_with_args,
 				args.push_back(std::string());
 				while (1)
 				{
+					skip_spaces();
 					tok = next_token(true);
 					if (tok == ")" || tok == "}" || tok == "]")
 						level--;
-- 
2.30.2