From 874c693228f1f8d82ebad52e8889fb3e125d23d4 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 22 May 2023 15:58:52 +0100 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index f4a44661e..1f42ecc14 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -731,7 +731,7 @@ on context after decoding of the Scalar suffix: | Field Name | Field bits | Description | |------------|------------|----------------------------------------| | ELWIDTH | `4:5` | Element Width | -| ELWIDTH_SRC | `6:7` | Element Width for Source | +| ELWIDTH_SRC | `6:7` | Element Width for Source (or MASK_SRC in 2PM) | | EXTRA | `10:18` | Register Extra encoding | | MODE | `19:23` | changes Vector behaviour | @@ -894,6 +894,9 @@ Additionally Programmers should avoid using r3 r10 or r30 as destination registers when these are also used as a Predicate Mask. Doing so is again UNDEFINED behaviour. +Usually in 2P `MASK_SRC` is exclusively in the EXTRA area. However for +LD/ST-Indexed a different Encoding is required, designated `2PM`. + ### Integer Predication (MASKMODE=0) When the predicate mode bit is zero the 3 bits are interpreted as below. @@ -916,7 +919,6 @@ following meaning: r10 and r30 are at the high end of temporary and unused registers, so as not to interfere with register allocation from ABIs. - ### CR-based Predication (MASKMODE=1) When the predicate mode bit is one the 3 bits are interpreted as below. @@ -986,6 +988,13 @@ some compromises have to be made. * `RM-2P-1S1D` Twin Predication (src=1, dest=1) * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed) * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update +* `RM-2PM-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed) +* `RM-2PM-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update + +The `2PM` designation uses bits 6 and 7 as well as the 9 EXTRA bits +in order to extend two registers to +EXTRA3, sacrificing destination elwidths in the process. +`MASK_SRC` has a different encoding in `2PM`. ### RM-1P-3S1D @@ -1100,6 +1109,24 @@ RM-2P-2S1D and the src spec for RA is also used for the same RA as a dest. Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing. +### RM-2PM-2S1D/1S2D/3S + +The primary purpose for this encoding is for Twin Predication on LOAD +and STORE operations providing EXTRA3 for RT, RA and RS. +see [[sv/ldst]] for detailed analysis. + +**RM-2PM-2S1D:** + +RT or RS requires EXTRA3, RA requires EXTRA3, but for RB EXTRA2 will +suffice. `MASK_SRC` may be read from the bits normally used for dest-elwidth. + +| Field Name | Field bits | Description | +|------------|------------|----------------------------| +| Rdest_EXTRA3 | `10:12` | extends Rdest (R\*\_EXTRA2 Encoding) | +| Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 (R\*\_EXTRA2 Encoding) | +| Rsrc2_EXTRA2 | `16:17` | extends Rsrc2 (R\*\_EXTRA2 Encoding) | +| MASK_SRC | `6:7,18` | Execution Mask for Source | + ## R\*\_EXTRA2/3 EXTRA is the means by which two things are achieved: -- 2.30.2