From 8750299a420af76cebd3067f6f603eacde06ae06 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Tue, 9 Feb 2016 14:51:28 -0800 Subject: [PATCH] nir: Remove the const_offset from nir_tex_instr When NIR was originally drafted, there was no easy way to determine if something was constant or not. The result was that we had lots of special-casing for constant values such as this. Now that load_const instructions are SSA-only, it's really easy to find constants and this isn't really needed anymore. Reviewed-by: Connor Abbott Reviewed-by: Rob Clark --- src/compiler/nir/glsl_to_nir.cpp | 16 ++++-------- src/compiler/nir/nir.h | 3 --- src/compiler/nir/nir_clone.c | 1 - src/compiler/nir/nir_instr_set.c | 3 --- src/compiler/nir/nir_print.c | 14 ---------- .../drivers/freedreno/ir3/ir3_compiler_nir.c | 15 ----------- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 26 ++++++++----------- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 21 ++++++++------- 8 files changed, 27 insertions(+), 72 deletions(-) diff --git a/src/compiler/nir/glsl_to_nir.cpp b/src/compiler/nir/glsl_to_nir.cpp index ee1a0cb9348..a23fba75010 100644 --- a/src/compiler/nir/glsl_to_nir.cpp +++ b/src/compiler/nir/glsl_to_nir.cpp @@ -1825,7 +1825,7 @@ nir_visitor::visit(ir_texture *ir) num_srcs++; if (ir->shadow_comparitor != NULL) num_srcs++; - if (ir->offset != NULL && ir->offset->as_constant() == NULL) + if (ir->offset != NULL) num_srcs++; nir_tex_instr *instr = nir_tex_instr_create(this->shader, num_srcs); @@ -1882,16 +1882,10 @@ nir_visitor::visit(ir_texture *ir) /* we don't support multiple offsets yet */ assert(ir->offset->type->is_vector() || ir->offset->type->is_scalar()); - ir_constant *const_offset = ir->offset->as_constant(); - if (const_offset != NULL) { - for (unsigned i = 0; i < const_offset->type->vector_elements; i++) - instr->const_offset[i] = const_offset->value.i[i]; - } else { - instr->src[src_number].src = - nir_src_for_ssa(evaluate_rvalue(ir->offset)); - instr->src[src_number].src_type = nir_tex_src_offset; - src_number++; - } + instr->src[src_number].src = + nir_src_for_ssa(evaluate_rvalue(ir->offset)); + instr->src[src_number].src_type = nir_tex_src_offset; + src_number++; } switch (ir->op) { diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 8085341b552..cccb3a41da5 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -1010,9 +1010,6 @@ typedef struct { */ bool is_new_style_shadow; - /* constant offset - must be 0 if the offset source is used */ - int const_offset[4]; - /* gather component selector */ unsigned component : 2; diff --git a/src/compiler/nir/nir_clone.c b/src/compiler/nir/nir_clone.c index a666d8ee451..b6bb5fe5668 100644 --- a/src/compiler/nir/nir_clone.c +++ b/src/compiler/nir/nir_clone.c @@ -355,7 +355,6 @@ clone_tex(clone_state *state, const nir_tex_instr *tex) ntex->is_array = tex->is_array; ntex->is_shadow = tex->is_shadow; ntex->is_new_style_shadow = tex->is_new_style_shadow; - memcpy(ntex->const_offset, tex->const_offset, sizeof(ntex->const_offset)); ntex->component = tex->component; ntex->texture_index = tex->texture_index; diff --git a/src/compiler/nir/nir_instr_set.c b/src/compiler/nir/nir_instr_set.c index c3cf2579be7..159ded0e72b 100644 --- a/src/compiler/nir/nir_instr_set.c +++ b/src/compiler/nir/nir_instr_set.c @@ -152,7 +152,6 @@ hash_tex(uint32_t hash, const nir_tex_instr *instr) hash = HASH(hash, instr->is_array); hash = HASH(hash, instr->is_shadow); hash = HASH(hash, instr->is_new_style_shadow); - hash = HASH(hash, instr->const_offset); unsigned component = instr->component; hash = HASH(hash, component); hash = HASH(hash, instr->texture_index); @@ -303,8 +302,6 @@ nir_instrs_equal(const nir_instr *instr1, const nir_instr *instr2) tex1->is_array != tex2->is_array || tex1->is_shadow != tex2->is_shadow || tex1->is_new_style_shadow != tex2->is_new_style_shadow || - memcmp(tex1->const_offset, tex2->const_offset, - sizeof(tex1->const_offset)) != 0 || tex1->component != tex2->component || tex1->texture_index != tex2->texture_index || tex1->texture_array_size != tex2->texture_array_size || diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c index d9d75c2e8df..8ccaf8a0edb 100644 --- a/src/compiler/nir/nir_print.c +++ b/src/compiler/nir/nir_print.c @@ -637,20 +637,6 @@ print_tex_instr(nir_tex_instr *instr, print_state *state) fprintf(fp, ", "); } - bool has_nonzero_offset = false; - for (unsigned i = 0; i < 4; i++) { - if (instr->const_offset[i] != 0) { - has_nonzero_offset = true; - break; - } - } - - if (has_nonzero_offset) { - fprintf(fp, "[%i %i %i %i] (offset), ", - instr->const_offset[0], instr->const_offset[1], - instr->const_offset[2], instr->const_offset[3]); - } - if (instr->op == nir_texop_tg4) { fprintf(fp, "%u (gather_component), ", instr->component); } diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c index 63dd1700f9c..ffa75775505 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c @@ -1434,21 +1434,6 @@ emit_tex(struct ir3_compile *ctx, nir_tex_instr *tex) tex_info(tex, &flags, &coords); - if (!has_off) { - /* could still have a constant offset: */ - if (tex->const_offset[0] || tex->const_offset[1] || - tex->const_offset[2] || tex->const_offset[3]) { - off = const_off; - - off[0] = create_immed(b, tex->const_offset[0]); - off[1] = create_immed(b, tex->const_offset[1]); - off[2] = create_immed(b, tex->const_offset[2]); - off[3] = create_immed(b, tex->const_offset[3]); - - has_off = true; - } - } - /* scale up integer coords for TXF based on the LOD */ if (ctx->unminify_coords && (opc == OPC_ISAML)) { assert(has_lod); diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index ade5b46928d..1fc21e474a7 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -2951,7 +2951,6 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr) instr->is_array; int lod_components = 0; - int UNUSED offset_components = 0; fs_reg coordinate, shadow_comparitor, lod, lod2, sample_index, mcs, tex_offset; @@ -2999,13 +2998,18 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr) case nir_tex_src_ms_index: sample_index = retype(src, BRW_REGISTER_TYPE_UD); break; - case nir_tex_src_offset: - tex_offset = retype(src, BRW_REGISTER_TYPE_D); - if (instr->is_array) - offset_components = instr->coord_components - 1; - else - offset_components = instr->coord_components; + + case nir_tex_src_offset: { + nir_const_value *const_offset = + nir_src_as_const_value(instr->src[i].src); + if (const_offset) { + tex_offset = brw_imm_ud(brw_texture_offset(const_offset->i, 3)); + } else { + tex_offset = retype(src, BRW_REGISTER_TYPE_D); + } break; + } + case nir_tex_src_projector: unreachable("should be lowered"); @@ -3049,14 +3053,6 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr) } } - for (unsigned i = 0; i < 3; i++) { - if (instr->const_offset[i] != 0) { - assert(offset_components == 0); - tex_offset = brw_imm_ud(brw_texture_offset(instr->const_offset, 3)); - break; - } - } - enum glsl_base_type dest_base_type = brw_glsl_base_type_for_nir_type (instr->dest_type); diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index ca6a9def7ad..74ec4f0e87f 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp @@ -1657,6 +1657,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) dst_reg dest = get_nir_dest(instr->dest, instr->dest_type); /* Load the texture operation sources */ + uint32_t constant_offset = 0; for (unsigned i = 0; i < instr->num_srcs; i++) { switch (instr->src[i].src_type) { case nir_tex_src_comparitor: @@ -1713,9 +1714,17 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) break; } - case nir_tex_src_offset: - offset_value = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, 2); + case nir_tex_src_offset: { + nir_const_value *const_offset = + nir_src_as_const_value(instr->src[i].src); + if (const_offset) { + constant_offset = brw_texture_offset(const_offset->i, 3); + } else { + offset_value = + get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, 2); + } break; + } case nir_tex_src_texture_offset: { /* The highest texture which may be used by this operation is @@ -1771,14 +1780,6 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) } } - uint32_t constant_offset = 0; - for (unsigned i = 0; i < 3; i++) { - if (instr->const_offset[i] != 0) { - constant_offset = brw_texture_offset(instr->const_offset, 3); - break; - } - } - /* Stuff the channel select bits in the top of the texture offset */ if (instr->op == nir_texop_tg4) { if (instr->component == 1 && -- 2.30.2