From 879721aa141ed4641dac61e1812cdfcb1e8f4b74 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 27 Jun 2021 14:26:09 +0100 Subject: [PATCH] override logic for getting FRS in SVP64 FFT mode --- src/openpower/decoder/isa/caller.py | 4 ++++ src/openpower/decoder/power_decoder2.py | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index d1a77a2a..3e9be726 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -372,6 +372,7 @@ def get_predcr(crl, mask, vl): return mask +# TODO, really should just be using PowerDecoder2 def get_pdecode_idx_in(dec2, name): op = dec2.dec.op in1_sel = yield op.in1_sel @@ -433,6 +434,7 @@ def get_pdecode_idx_in(dec2, name): return None, False +# TODO, really should just be using PowerDecoder2 def get_pdecode_cr_out(dec2, name): op = dec2.dec.op out_sel = yield op.cr_out @@ -456,6 +458,7 @@ def get_pdecode_cr_out(dec2, name): return None, False +# TODO, really should just be using PowerDecoder2 def get_pdecode_idx_out(dec2, name): op = dec2.dec.op out_sel = yield op.out_sel @@ -485,6 +488,7 @@ def get_pdecode_idx_out(dec2, name): return None, False +# TODO, really should just be using PowerDecoder2 def get_pdecode_idx_out2(dec2, name): # check first if register is activated for write out_ok = yield dec2.e.write_ea.ok diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index e8f6cceb..07303840 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -1288,6 +1288,22 @@ class PowerDecode2(PowerDecodeSubset): comb += self.in3_isvec.eq(in3_svdec.isvec) comb += self.o_isvec.eq(o_svdec.isvec) comb += self.o2_isvec.eq(o2_svdec.isvec) + + # urrr... don't ask... the implicit register FRS in FFT mode + # "tracks" FRT exactly except it's offset by VL. rather than + # mess up the above with if-statements, override it here + with m.If(dec_o2.reg_out.ok & self.use_svp64_fft): + svdec = o_svdec # yes take source as o_svdec... + with m.If(svdec.isvec): + # reverse gear goes the opposite way + with m.If(self.rm_dec.reverse_gear): + comb += to_reg.data.eq(vl+svdec.reg_out+(vl-1-dststep)) + with m.Else(): + comb += to_reg.data.eq(vl+dststep+svdec.reg_out) + # ... but write to *second* output + comb += self.o2_isvec.eq(svdec.isvec) + comb += o2_svdec.idx.eq(self.op_get("sv_out")) + # TODO add SPRs here. must be True when *all* are scalar l = map(lambda svdec: svdec.isvec, [in1_svdec, in2_svdec, in3_svdec, crin_svdec, crin_svdec_b, crin_svdec_o]) -- 2.30.2