From 87a1cb697937fa01405b0a57470ee69b9cf19998 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Fri, 19 Aug 2016 03:15:41 -0700 Subject: [PATCH] i965: Move the hiz_op enum to blorp Signed-off-by: Jason Ekstrand Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/blorp.c | 3 +-- src/mesa/drivers/dri/i965/blorp.h | 20 +++++++++++++++-- src/mesa/drivers/dri/i965/blorp_priv.h | 2 +- src/mesa/drivers/dri/i965/brw_blorp.c | 12 +++++----- src/mesa/drivers/dri/i965/brw_blorp.h | 2 +- src/mesa/drivers/dri/i965/brw_clear.c | 4 ++-- src/mesa/drivers/dri/i965/brw_context.h | 2 +- src/mesa/drivers/dri/i965/gen8_depth_state.c | 12 +++++----- src/mesa/drivers/dri/i965/genX_blorp_exec.h | 18 +++++++-------- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 18 +++++++-------- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +- src/mesa/drivers/dri/i965/intel_resolve_map.c | 2 +- src/mesa/drivers/dri/i965/intel_resolve_map.h | 22 +++---------------- 13 files changed, 59 insertions(+), 60 deletions(-) diff --git a/src/mesa/drivers/dri/i965/blorp.c b/src/mesa/drivers/dri/i965/blorp.c index 20477dd086b..16ccd34aab1 100644 --- a/src/mesa/drivers/dri/i965/blorp.c +++ b/src/mesa/drivers/dri/i965/blorp.c @@ -144,7 +144,6 @@ void brw_blorp_params_init(struct brw_blorp_params *params) { memset(params, 0, sizeof(*params)); - params->hiz_op = GEN6_HIZ_OP_NONE; params->num_draw_buffers = 1; params->num_layers = 1; } @@ -238,7 +237,7 @@ brw_blorp_compile_nir_shader(struct blorp_context *blorp, struct nir_shader *nir void blorp_gen6_hiz_op(struct blorp_batch *batch, struct brw_blorp_surf *surf, unsigned level, unsigned layer, - enum gen6_hiz_op op) + enum blorp_hiz_op op) { struct brw_blorp_params params; brw_blorp_params_init(¶ms); diff --git a/src/mesa/drivers/dri/i965/blorp.h b/src/mesa/drivers/dri/i965/blorp.h index 87867779d8d..27f22c9d34c 100644 --- a/src/mesa/drivers/dri/i965/blorp.h +++ b/src/mesa/drivers/dri/i965/blorp.h @@ -27,7 +27,6 @@ #include #include "isl/isl.h" -#include "intel_resolve_map.h" /* needed for enum gen6_hiz_op */ struct brw_context; struct brw_wm_prog_key; @@ -128,10 +127,27 @@ void brw_blorp_ccs_resolve(struct blorp_batch *batch, struct brw_blorp_surf *surf, enum isl_format format); +/** + * For an overview of the HiZ operations, see the following sections of the + * Sandy Bridge PRM, Volume 1, Part2: + * - 7.5.3.1 Depth Buffer Clear + * - 7.5.3.2 Depth Buffer Resolve + * - 7.5.3.3 Hierarchical Depth Buffer Resolve + * + * Of these, two get entered in the resolve map as needing to be done to the + * buffer: depth resolve and hiz resolve. + */ +enum blorp_hiz_op { + BLORP_HIZ_OP_NONE, + BLORP_HIZ_OP_DEPTH_CLEAR, + BLORP_HIZ_OP_DEPTH_RESOLVE, + BLORP_HIZ_OP_HIZ_RESOLVE, +}; + void blorp_gen6_hiz_op(struct blorp_batch *batch, struct brw_blorp_surf *surf, unsigned level, unsigned layer, - enum gen6_hiz_op op); + enum blorp_hiz_op op); #ifdef __cplusplus } /* end extern "C" */ diff --git a/src/mesa/drivers/dri/i965/blorp_priv.h b/src/mesa/drivers/dri/i965/blorp_priv.h index 36ff637a79f..a25291b7674 100644 --- a/src/mesa/drivers/dri/i965/blorp_priv.h +++ b/src/mesa/drivers/dri/i965/blorp_priv.h @@ -174,7 +174,7 @@ struct brw_blorp_params uint32_t depth_format; struct brw_blorp_surface_info src; struct brw_blorp_surface_info dst; - enum gen6_hiz_op hiz_op; + enum blorp_hiz_op hiz_op; enum blorp_fast_clear_op fast_clear_op; bool color_write_disable[4]; struct brw_blorp_wm_inputs wm_inputs; diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index e59c26e7883..b2b3f01e8ff 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -839,7 +839,7 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt) static void gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, - unsigned int level, unsigned int layer, enum gen6_hiz_op op) + unsigned int level, unsigned int layer, enum blorp_hiz_op op) { intel_miptree_check_level_layer(mt, level, layer); intel_miptree_used_for_rendering(mt); @@ -867,21 +867,21 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, */ void intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, - unsigned int level, unsigned int layer, enum gen6_hiz_op op) + unsigned int level, unsigned int layer, enum blorp_hiz_op op) { const char *opname = NULL; switch (op) { - case GEN6_HIZ_OP_DEPTH_RESOLVE: + case BLORP_HIZ_OP_DEPTH_RESOLVE: opname = "depth resolve"; break; - case GEN6_HIZ_OP_HIZ_RESOLVE: + case BLORP_HIZ_OP_HIZ_RESOLVE: opname = "hiz ambiguate"; break; - case GEN6_HIZ_OP_DEPTH_CLEAR: + case BLORP_HIZ_OP_DEPTH_CLEAR: opname = "depth clear"; break; - case GEN6_HIZ_OP_NONE: + case BLORP_HIZ_OP_NONE: opname = "noop?"; break; } diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h index 1aa19520218..53a732ea27e 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.h +++ b/src/mesa/drivers/dri/i965/brw_blorp.h @@ -58,7 +58,7 @@ brw_blorp_resolve_color(struct brw_context *brw, void intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, - unsigned int level, unsigned int layer, enum gen6_hiz_op op); + unsigned int level, unsigned int layer, enum blorp_hiz_op op); void gen6_blorp_exec(struct blorp_batch *batch, const struct brw_blorp_params *params); diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index 18b8fcbe200..0d64d8914d6 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -187,11 +187,11 @@ brw_fast_clear_depth(struct gl_context *ctx) for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) { intel_hiz_exec(brw, mt, depth_irb->mt_level, depth_irb->mt_layer + layer, - GEN6_HIZ_OP_DEPTH_CLEAR); + BLORP_HIZ_OP_DEPTH_CLEAR); } } else { intel_hiz_exec(brw, mt, depth_irb->mt_level, depth_irb->mt_layer, - GEN6_HIZ_OP_DEPTH_CLEAR); + BLORP_HIZ_OP_DEPTH_CLEAR); } if (brw->gen == 6) { diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index da80e348a7d..a76b25f0b96 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1848,7 +1848,7 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw, uint32_t tile_x, uint32_t tile_y); void gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, - unsigned int level, unsigned int layer, enum gen6_hiz_op op); + unsigned int level, unsigned int layer, enum blorp_hiz_op op); uint32_t get_hw_prim_for_gl_prim(int mode); diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c index a780da6b376..4930991e3c0 100644 --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c @@ -398,9 +398,9 @@ const struct brw_tracked_state gen8_pma_fix = { */ void gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, - unsigned int level, unsigned int layer, enum gen6_hiz_op op) + unsigned int level, unsigned int layer, enum blorp_hiz_op op) { - if (op == GEN6_HIZ_OP_NONE) + if (op == BLORP_HIZ_OP_NONE) return; /* Disable the PMA stall fix since we're about to do a HiZ operation. */ @@ -468,16 +468,16 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t dw1 = 0; switch (op) { - case GEN6_HIZ_OP_DEPTH_RESOLVE: + case BLORP_HIZ_OP_DEPTH_RESOLVE: dw1 |= GEN8_WM_HZ_DEPTH_RESOLVE; break; - case GEN6_HIZ_OP_HIZ_RESOLVE: + case BLORP_HIZ_OP_HIZ_RESOLVE: dw1 |= GEN8_WM_HZ_HIZ_RESOLVE; break; - case GEN6_HIZ_OP_DEPTH_CLEAR: + case BLORP_HIZ_OP_DEPTH_CLEAR: dw1 |= GEN8_WM_HZ_DEPTH_CLEAR; break; - case GEN6_HIZ_OP_NONE: + case BLORP_HIZ_OP_NONE: unreachable("Should not get here."); } diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.h b/src/mesa/drivers/dri/i965/genX_blorp_exec.h index 7ef6a1dd0ac..649c3db8780 100644 --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.h +++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.h @@ -566,16 +566,16 @@ blorp_emit_ps_config(struct blorp_batch *batch, blorp_emit(batch, GENX(3DSTATE_WM), wm) { switch (params->hiz_op) { - case GEN6_HIZ_OP_DEPTH_CLEAR: + case BLORP_HIZ_OP_DEPTH_CLEAR: wm.DepthBufferClear = true; break; - case GEN6_HIZ_OP_DEPTH_RESOLVE: + case BLORP_HIZ_OP_DEPTH_RESOLVE: wm.DepthBufferResolveEnable = true; break; - case GEN6_HIZ_OP_HIZ_RESOLVE: + case BLORP_HIZ_OP_HIZ_RESOLVE: wm.HierarchicalDepthBufferResolveEnable = true; break; - case GEN6_HIZ_OP_NONE: + case BLORP_HIZ_OP_NONE: break; default: unreachable("not reached"); @@ -651,16 +651,16 @@ blorp_emit_ps_config(struct blorp_batch *batch, batch->blorp->isl_dev->info->max_wm_threads - 1; switch (params->hiz_op) { - case GEN6_HIZ_OP_DEPTH_CLEAR: + case BLORP_HIZ_OP_DEPTH_CLEAR: wm.DepthBufferClear = true; break; - case GEN6_HIZ_OP_DEPTH_RESOLVE: + case BLORP_HIZ_OP_DEPTH_RESOLVE: wm.DepthBufferResolveEnable = true; break; - case GEN6_HIZ_OP_HIZ_RESOLVE: + case BLORP_HIZ_OP_HIZ_RESOLVE: wm.HierarchicalDepthBufferResolveEnable = true; break; - case GEN6_HIZ_OP_NONE: + case BLORP_HIZ_OP_NONE: break; default: unreachable("not reached"); @@ -850,7 +850,7 @@ blorp_emit_depth_stencil_state(struct blorp_batch *batch, .DepthBufferWriteEnable = true, }; - if (params->hiz_op == GEN6_HIZ_OP_DEPTH_RESOLVE) { + if (params->hiz_op == BLORP_HIZ_OP_DEPTH_RESOLVE) { ds.DepthTestEnable = true; ds.DepthTestFunction = COMPAREFUNCTION_NEVER; } diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index c33d8fcbf2c..08beea86447 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -2004,7 +2004,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw, exec_node_init(&m->link); m->level = level; m->layer = layer; - m->need = GEN6_HIZ_OP_HIZ_RESOLVE; + m->need = BLORP_HIZ_OP_HIZ_RESOLVE; exec_list_push_tail(&mt->hiz_map, &m->link); } @@ -2032,7 +2032,7 @@ intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt, return; intel_resolve_map_set(&mt->hiz_map, - level, layer, GEN6_HIZ_OP_HIZ_RESOLVE); + level, layer, BLORP_HIZ_OP_HIZ_RESOLVE); } @@ -2045,7 +2045,7 @@ intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt, return; intel_resolve_map_set(&mt->hiz_map, - level, layer, GEN6_HIZ_OP_DEPTH_RESOLVE); + level, layer, BLORP_HIZ_OP_DEPTH_RESOLVE); } void @@ -2065,7 +2065,7 @@ intel_miptree_slice_resolve(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level, uint32_t layer, - enum gen6_hiz_op need) + enum blorp_hiz_op need) { intel_miptree_check_level_layer(mt, level, layer); @@ -2087,7 +2087,7 @@ intel_miptree_slice_resolve_hiz(struct brw_context *brw, uint32_t layer) { return intel_miptree_slice_resolve(brw, mt, level, layer, - GEN6_HIZ_OP_HIZ_RESOLVE); + BLORP_HIZ_OP_HIZ_RESOLVE); } bool @@ -2097,13 +2097,13 @@ intel_miptree_slice_resolve_depth(struct brw_context *brw, uint32_t layer) { return intel_miptree_slice_resolve(brw, mt, level, layer, - GEN6_HIZ_OP_DEPTH_RESOLVE); + BLORP_HIZ_OP_DEPTH_RESOLVE); } static bool intel_miptree_all_slices_resolve(struct brw_context *brw, struct intel_mipmap_tree *mt, - enum gen6_hiz_op need) + enum blorp_hiz_op need) { bool did_resolve = false; @@ -2124,7 +2124,7 @@ intel_miptree_all_slices_resolve_hiz(struct brw_context *brw, struct intel_mipmap_tree *mt) { return intel_miptree_all_slices_resolve(brw, mt, - GEN6_HIZ_OP_HIZ_RESOLVE); + BLORP_HIZ_OP_HIZ_RESOLVE); } bool @@ -2132,7 +2132,7 @@ intel_miptree_all_slices_resolve_depth(struct brw_context *brw, struct intel_mipmap_tree *mt) { return intel_miptree_all_slices_resolve(brw, mt, - GEN6_HIZ_OP_DEPTH_RESOLVE); + BLORP_HIZ_OP_DEPTH_RESOLVE); } diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index e7d4de06a28..27dbfa49e03 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -1022,7 +1022,7 @@ intel_miptree_unmap(struct brw_context *brw, void intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, - unsigned int level, unsigned int layer, enum gen6_hiz_op op); + unsigned int level, unsigned int layer, enum blorp_hiz_op op); #ifdef __cplusplus } diff --git a/src/mesa/drivers/dri/i965/intel_resolve_map.c b/src/mesa/drivers/dri/i965/intel_resolve_map.c index 3df4b882b05..26eac8bc65e 100644 --- a/src/mesa/drivers/dri/i965/intel_resolve_map.c +++ b/src/mesa/drivers/dri/i965/intel_resolve_map.c @@ -35,7 +35,7 @@ void intel_resolve_map_set(struct exec_list *resolve_map, uint32_t level, uint32_t layer, - enum gen6_hiz_op need) + enum blorp_hiz_op need) { foreach_list_typed(struct intel_resolve_map, map, link, resolve_map) { if (map->level == level && map->layer == layer) { diff --git a/src/mesa/drivers/dri/i965/intel_resolve_map.h b/src/mesa/drivers/dri/i965/intel_resolve_map.h index 726b287722a..672a4aaba7c 100644 --- a/src/mesa/drivers/dri/i965/intel_resolve_map.h +++ b/src/mesa/drivers/dri/i965/intel_resolve_map.h @@ -24,29 +24,13 @@ #pragma once #include +#include "blorp.h" #include "compiler/glsl/list.h" #ifdef __cplusplus extern "C" { #endif -/** - * For an overview of the HiZ operations, see the following sections of the - * Sandy Bridge PRM, Volume 1, Part2: - * - 7.5.3.1 Depth Buffer Clear - * - 7.5.3.2 Depth Buffer Resolve - * - 7.5.3.3 Hierarchical Depth Buffer Resolve - * - * Of these, two get entered in the resolve map as needing to be done to the - * buffer: depth resolve and hiz resolve. - */ -enum gen6_hiz_op { - GEN6_HIZ_OP_DEPTH_CLEAR, - GEN6_HIZ_OP_DEPTH_RESOLVE, - GEN6_HIZ_OP_HIZ_RESOLVE, - GEN6_HIZ_OP_NONE, -}; - /** * \brief Map of miptree slices to needed resolves. * @@ -78,14 +62,14 @@ struct intel_resolve_map { uint32_t level; uint32_t layer; - enum gen6_hiz_op need; + enum blorp_hiz_op need; }; void intel_resolve_map_set(struct exec_list *resolve_map, uint32_t level, uint32_t layer, - enum gen6_hiz_op need); + enum blorp_hiz_op need); struct intel_resolve_map * intel_resolve_map_get(struct exec_list *resolve_map, -- 2.30.2