From 87b173b755d140f65c5e2228fc071fb21ff10824 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 16 May 2022 19:39:00 -0700 Subject: [PATCH] scale images to 100% --- openpower/sv/bitmanip/grev_gorc_design.mdwn | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openpower/sv/bitmanip/grev_gorc_design.mdwn b/openpower/sv/bitmanip/grev_gorc_design.mdwn index dbb71d4a4..b2e4ee666 100644 --- a/openpower/sv/bitmanip/grev_gorc_design.mdwn +++ b/openpower/sv/bitmanip/grev_gorc_design.mdwn @@ -2,17 +2,17 @@ The design is derived from a circuit for GRev made with muxes: - + First, we convert that circuit to use And-Or-Invert gates, since that's an efficient way the muxes can be implemented: - + Notice how each And-Or-Invert has both a bit of `SH` and `~SH` as inputs? Those can be converted to separate inputs, controlled by the bits of `SH` using the instruction's immediate as a pair of 2-bit look-up-tables. This requires 4-bits of immediate. This gives us our final design: - + Notice how this still has an overall circuit latency that is essentially equivalent to grev's latency (or shift/rotate's latency). Also notice how this circuit allows specifying much more than just `grev` or `gorc` instructions. A final layer of XOR gates can be added at the input and output, allowing it to function as a `gandc` instruction too, requiring a total of 6-bits of immediate. -- 2.30.2