From 87c34e8c810dc4f148be1af8b238b610dc808141 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Jun 2020 18:54:41 +0100 Subject: [PATCH] write-enable sram into common wen signal, use that to enable wen from sel --- nmigen_soc/wishbone/sram.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py index c518ff9..3007172 100644 --- a/nmigen_soc/wishbone/sram.py +++ b/nmigen_soc/wishbone/sram.py @@ -1,4 +1,4 @@ -from nmigen import Elaboratable, Memory, Module +from nmigen import Elaboratable, Memory, Module, Signal from nmigen.utils import log2_int from nmigen_soc.wishbone.bus import Interface @@ -90,9 +90,10 @@ class SRAM(Elaboratable): n_bussel = self.bus.sel.shape()[0] assert n_wrport == n_bussel, "bus enable count %d " \ "must match memory wen count %d" % (n_wrport, n_bussel) - for i in range(n_wrport): - m.d.comb += wrport.en[i].eq(self.bus.cyc & self.bus.stb & - self.bus.we & self.bus.sel[i]) + wen = Signal() + m.d.comb += wen.eq(self.bus.cyc & self.bus.stb & self.bus.we) + with m.If(wen): + m.d.comb += wrport.en.eq(self.bus.sel) # generate ack m.d.sync += self.bus.ack.eq(0) -- 2.30.2