From 87e7318e31ead7c6cb939aed7df5d28bfe05ef82 Mon Sep 17 00:00:00 2001 From: Staf Verhaegen Date: Tue, 10 Dec 2019 21:31:16 +0100 Subject: [PATCH] Made STATE and NEXT_STATE internal to c4m_jtag_tap_fsm. This also makes the STATE_TYPE type internal to c4m_jtag_tap_fsm. --- c4m/nmigen/jtag/tap.py | 12 +- c4m/vhdl/jtag/c4m_jtag_idblock.vhdl | 41 +++--- c4m/vhdl/jtag/c4m_jtag_ioblock.vhdl | 22 ++-- c4m/vhdl/jtag/c4m_jtag_irblock.vhdl | 49 +++---- c4m/vhdl/jtag/c4m_jtag_pkg.vhdl | 68 ++++------ c4m/vhdl/jtag/c4m_jtag_tap_controller.vhdl | 64 ++++----- c4m/vhdl/jtag/c4m_jtag_tap_fsm.vhdl | 131 +++++++++++-------- test/cocotb/controller/Makefile | 1 + test/cocotb/dual_parallel/Makefile | 1 + test/cocotb/dual_parallel/dual_parallel.vhdl | 12 +- test/rtl/vhdl/idcode.vhdl | 6 +- 11 files changed, 202 insertions(+), 205 deletions(-) diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py index fdcf762..c12eabf 100755 --- a/c4m/nmigen/jtag/tap.py +++ b/c4m/nmigen/jtag/tap.py @@ -97,9 +97,9 @@ class TAP(Elaboratable): -- The FSM state indicators RESET: out std_logic; - DRCAPTURE: out std_logic; - DRSHIFT: out std_logic; - DRUPDATE: out std_logic; + CAPTURE: out std_logic; + SHIFT: out std_logic; + UPDATE: out std_logic; -- The Instruction Register IR: out std_logic_vector({ir_width}-1 downto 0); @@ -134,9 +134,9 @@ class TAP(Elaboratable): TDO => TDO, TRST_N => TRST_N, RESET => RESET, - DRCAPTURE => DRCAPTURE, - DRSHIFT => DRSHIFT, - DRUPDATE => DRUPDATE, + CAPTURE => CAPTURE, + SHIFT => SHIFT, + UPDATE => UPDATE, IR => IR, CORE_IN => CORE_IN, CORE_EN => CORE_EN, diff --git a/c4m/vhdl/jtag/c4m_jtag_idblock.vhdl b/c4m/vhdl/jtag/c4m_jtag_idblock.vhdl index 303959a..a8c4ac9 100644 --- a/c4m/vhdl/jtag/c4m_jtag_idblock.vhdl +++ b/c4m/vhdl/jtag/c4m_jtag_idblock.vhdl @@ -20,13 +20,13 @@ entity c4m_jtag_idblock is TDO: out std_logic; TDO_EN: out std_logic := '0'; - -- JTAG state - STATE: in TAPSTATE_TYPE; - NEXT_STATE: in TAPSTATE_TYPE; - DRSTATE: in std_logic; - -- The instruction - IR: in std_logic_vector(IR_WIDTH-1 downto 0) + IR: in std_logic_vector(IR_WIDTH-1 downto 0); + + -- actions + CAPTURE: in std_logic; + SHIFT: in std_logic; + UPDATE: in std_logic ); end c4m_jtag_idblock; @@ -42,31 +42,22 @@ begin process (TCK) begin if rising_edge(TCK) then - if DRSTATE = '1' then - case STATE is - when Capture => - SR_ID <= IDCODE; - - when Shift => - if IR = CMD_IDCODE then - SR_ID(30 downto 0) <= SR_ID(31 downto 1); - SR_ID(31) <= TDI; - elsif IR = CMD_BYPASS then - SR_ID(0) <= TDI; - else - null; - end if; - - when others => - null; - end case; + if CAPTURE = '1' then + SR_ID <= IDCODE; + elsif SHIFT = '1' then + if IR = CMD_IDCODE then + SR_ID(30 downto 0) <= SR_ID(31 downto 1); + SR_ID(31) <= TDI; + elsif IR = CMD_BYPASS then + SR_ID(0) <= TDI; + end if; end if; end if; end process; - EN_TDO <= STATE = Shift and DRSTATE = '1' and (IR = CMD_IDCODE or IR = CMD_BYPASS); TDO <= SR_ID(0) when EN_TDO else '0'; + EN_TDO <= SHIFT = '1' and (IR = CMD_IDCODE or IR = CMD_BYPASS); TDO_EN <= '1' when EN_TDO else '0'; end rtl; diff --git a/c4m/vhdl/jtag/c4m_jtag_ioblock.vhdl b/c4m/vhdl/jtag/c4m_jtag_ioblock.vhdl index 5990e3e..bb31327 100644 --- a/c4m/vhdl/jtag/c4m_jtag_ioblock.vhdl +++ b/c4m/vhdl/jtag/c4m_jtag_ioblock.vhdl @@ -17,14 +17,14 @@ entity c4m_jtag_ioblock is TDO: out std_logic; TDO_EN: out std_logic := '0'; - -- JTAG state - STATE: in TAPSTATE_TYPE; - NEXT_STATE: in TAPSTATE_TYPE; - DRSTATE: in std_logic; - -- The instruction IR: in std_logic_vector(IR_WIDTH-1 downto 0); + -- What action to perform + CAPTURE: in std_logic; + SHIFT: in std_logic; + UPDATE: in std_logic; + -- The I/O access ports CORE_OUT: in std_logic_vector(IOS-1 downto 0); CORE_IN: out std_logic_vector(IOS-1 downto 0); @@ -79,14 +79,14 @@ begin SR_Through; -- Set SAMPLEMODE - ISSAMPLECMD <= (IR = CMD_SAMPLEPRELOAD or IR = CMD_EXTEST) and DRSTATE = '1'; - SAMPLEMODE <= SR_Sample when ISSAMPLECMD and STATE = Capture else - SR_Update when ISSAMPLECMD and STATE = Update else - SR_Shift when ISSAMPLECMD and STATE = Shift else + ISSAMPLECMD <= (IR = CMD_SAMPLEPRELOAD or IR = CMD_EXTEST); + SAMPLEMODE <= SR_Sample when ISSAMPLECMD and CAPTURE = '1' else + SR_Update when ISSAMPLECMD and UPDATE = '1' else + SR_Shift when ISSAMPLECMD and SHIFT = '1' else SR_Normal; - TDO <= BDSR_OUT(0) when ISSAMPLECMD and STATE = Shift else + TDO <= BDSR_OUT(BDSR_IN'high) when ISSAMPLECMD and SHIFT = '1' else '0'; - TDO_EN <= '1' when ISSAMPLECMD and STATE = Shift else + TDO_EN <= '1' when ISSAMPLECMD and SHIFT = '1' else '0'; end rtl; diff --git a/c4m/vhdl/jtag/c4m_jtag_irblock.vhdl b/c4m/vhdl/jtag/c4m_jtag_irblock.vhdl index 8be483a..2157337 100644 --- a/c4m/vhdl/jtag/c4m_jtag_irblock.vhdl +++ b/c4m/vhdl/jtag/c4m_jtag_irblock.vhdl @@ -15,14 +15,15 @@ entity c4m_jtag_irblock is TDI: in std_logic; TDO: out std_logic; TDO_EN: out std_logic := '0'; - - -- JTAG state - STATE: in TAPSTATE_TYPE; - NEXT_STATE: in TAPSTATE_TYPE; - IRSTATE: in std_logic; -- instruction register - IR: out std_logic_vector(IR_WIDTH-1 downto 0) + IR: out std_logic_vector(IR_WIDTH-1 downto 0); + + -- actions + RESET: in std_logic; + CAPTURE: in std_logic; + SHIFT: in std_logic; + UPDATE: in std_logic ); end c4m_jtag_irblock; @@ -31,34 +32,26 @@ architecture rtl of c4m_jtag_irblock is constant CMD_IDCODE: std_logic_vector(IR_WIDTH-1 downto 0) := c4m_jtag_cmd_idcode(IR_WIDTH); begin - process (TCK, STATE) + process (TCK) begin - if STATE = TestLogicReset then + if rising_edge(TCK) then + if RESET = '1' then SHIFT_IR <= (others => '0'); IR <= CMD_IDCODE; - elsif rising_edge(TCK) then - if IRSTATE = '1' then - case STATE is - when Capture => - SHIFT_IR(1) <= '0'; - SHIFT_IR(0) <= '1'; - - when Shift => - SHIFT_IR(IR_WIDTH-2 downto 0) <= SHIFT_IR(IR_WIDTH-1 downto 1); - SHIFT_IR(IR_WIDTH-1) <= TDI; - - when Update => - IR <= SHIFT_IR; - - when others => - null; - end case; + elsif CAPTURE = '1' then + SHIFT_IR(1) <= '0'; + SHIFT_IR(0) <= '1'; + elsif SHIFT = '1' then + SHIFT_IR(IR_WIDTH-2 downto 0) <= SHIFT_IR(IR_WIDTH-1 downto 1); + SHIFT_IR(IR_WIDTH-1) <= TDI; + elsif UPDATE = '1' then + IR <= SHIFT_IR; end if; end if; end process; - TDO <= SHIFT_IR(0) when STATE = Shift and IRSTATE = '1' else - '0'; - TDO_EN <= '1' when STATE = Shift and IRSTATE = '1' else + TDO <= SHIFT_IR(0) when SHIFT = '1' else + 'X'; + TDO_EN <= '1' when SHIFT = '1' else '0'; end rtl; diff --git a/c4m/vhdl/jtag/c4m_jtag_pkg.vhdl b/c4m/vhdl/jtag/c4m_jtag_pkg.vhdl index 8bf4908..443a07c 100644 --- a/c4m/vhdl/jtag/c4m_jtag_pkg.vhdl +++ b/c4m/vhdl/jtag/c4m_jtag_pkg.vhdl @@ -3,18 +3,6 @@ library ieee; use ieee.std_logic_1164.ALL; package c4m_jtag is - type TAPSTATE_TYPE is ( - TestLogicReset, - RunTestIdle, - SelectDRScan, - SelectIRScan, - Capture, - Shift, - Exit1, - Pause, - Exit2, - Update - ); type SRIOMODE_TYPE is ( SR_Through, -- Connect core signal to pad signals SR_2Pad, -- Connect BD to pad @@ -41,10 +29,12 @@ package c4m_jtag is TRST_N: in std_logic; -- The state outputs - STATE: out TAPSTATE_TYPE; - NEXT_STATE: out TAPSTATE_TYPE; - DRSTATE: out std_logic; - IRSTATE: out std_logic + RESET: out std_logic; + ISDR: out std_logic; + ISIR: out std_logic; + CAPTURE: out std_logic; + SHIFT: out std_logic; + UPDATE: out std_logic ); end component c4m_jtag_tap_fsm; @@ -58,14 +48,15 @@ package c4m_jtag is TDI: in std_logic; TDO: out std_logic; TDO_EN: out std_logic; - - -- JTAG state - STATE: in TAPSTATE_TYPE; - NEXT_STATE: in TAPSTATE_TYPE; - IRSTATE: in std_logic; -- instruction register - IR: out std_logic_vector(IR_WIDTH-1 downto 0) + IR: out std_logic_vector(IR_WIDTH-1 downto 0); + + -- actions + RESET: in std_logic; + CAPTURE: in std_logic; + SHIFT: in std_logic; + UPDATE: in std_logic ); end component c4m_jtag_irblock; @@ -86,13 +77,13 @@ package c4m_jtag is TDO: out std_logic; TDO_EN: out std_logic; - -- JTAG state - STATE: in TAPSTATE_TYPE; - NEXT_STATE: in TAPSTATE_TYPE; - DRSTATE: in std_logic; - -- The instruction - IR: in std_logic_vector(IR_WIDTH-1 downto 0) + IR: in std_logic_vector(IR_WIDTH-1 downto 0); + + -- actions + CAPTURE: in std_logic; + SHIFT: in std_logic; + UPDATE: in std_logic ); end component c4m_jtag_idblock; @@ -131,14 +122,14 @@ package c4m_jtag is TDO: out std_logic; TDO_EN: out std_logic; - -- JTAG state - STATE: in TAPSTATE_TYPE; - NEXT_STATE: in TAPSTATE_TYPE; - DRSTATE: in std_logic; - -- The instruction IR: in std_logic_vector(IR_WIDTH-1 downto 0); + -- What action to perform + CAPTURE: in std_logic; + SHIFT: in std_logic; + UPDATE: in std_logic; + -- The I/O access ports CORE_OUT: in std_logic_vector(IOS-1 downto 0); CORE_IN: out std_logic_vector(IOS-1 downto 0); @@ -172,15 +163,14 @@ package c4m_jtag is TDO: out std_logic; TRST_N: in std_logic; - -- The FSM state indicators - RESET: out std_logic; -- In reset state - DRCAPTURE: out std_logic; -- In DR_Capture state - DRSHIFT: out std_logic; -- In DR_Shift state - DRUPDATE: out std_logic; -- In DR_Update state - -- The Instruction Register IR: out std_logic_vector(IR_WIDTH-1 downto 0); + -- The FSM state indicators + RESET: out std_logic; -- In reset state + CAPTURE: out std_logic; -- In DR_Capture state + SHIFT: out std_logic; -- In DR_Shift state + UPDATE: out std_logic; -- In DR_Update state -- The I/O access ports CORE_IN: out std_logic_vector(IOS-1 downto 0); CORE_EN: in std_logic_vector(IOS-1 downto 0); diff --git a/c4m/vhdl/jtag/c4m_jtag_tap_controller.vhdl b/c4m/vhdl/jtag/c4m_jtag_tap_controller.vhdl index 3ec8723..f29c8f8 100644 --- a/c4m/vhdl/jtag/c4m_jtag_tap_controller.vhdl +++ b/c4m/vhdl/jtag/c4m_jtag_tap_controller.vhdl @@ -25,15 +25,15 @@ entity c4m_jtag_tap_controller is TDO: out std_logic; TRST_N: in std_logic; - -- The FSM state indicators - RESET: out std_logic; - DRCAPTURE: out std_logic; - DRSHIFT: out std_logic; - DRUPDATE: out std_logic; - -- The Instruction Register IR: out std_logic_vector(IR_WIDTH-1 downto 0); + -- The FSM state indicators + RESET: out std_logic; + CAPTURE: out std_logic; + SHIFT: out std_logic; + UPDATE: out std_logic; + -- The I/O access ports CORE_IN: out std_logic_vector(IOS-1 downto 0); CORE_EN: in std_logic_vector(IOS-1 downto 0); @@ -47,10 +47,12 @@ entity c4m_jtag_tap_controller is end c4m_jtag_tap_controller; architecture rtl of c4m_jtag_tap_controller is - signal S_STATE: TAPSTATE_TYPE; - signal S_NEXT_STATE: TAPSTATE_TYPE; - signal S_IRSTATE: std_logic; - signal S_DRSTATE: std_logic; + signal S_RESET: std_logic; + signal S_ISIR: std_logic; + signal S_ISDR: std_logic; + signal S_CAPTURE: std_logic; + signal S_SHIFT: std_logic; + signal S_UPDATE: std_logic; signal S_IR: std_logic_vector(IR_WIDTH-1 downto 0); signal IR_TDO: std_logic; @@ -61,11 +63,10 @@ architecture rtl of c4m_jtag_tap_controller is signal IO_TDO_EN: std_logic; begin IR <= S_IR; - - RESET <= '1' when S_STATE = TestLogicReset else '0'; - DRCAPTURE <= '1' when S_STATE = Capture and S_DRSTATE = '1' else '0'; - DRSHIFT <= '1' when S_STATE = Shift and S_DRSTATE = '1' else '0'; - DRUPDATE <= '1' when S_STATE = Update and S_DRSTATE = '1' else '0'; + RESET <= S_RESET; + CAPTURE <= S_CAPTURE and S_ISDR; + SHIFT <= S_SHIFT and S_ISDR; + UPDATE <= S_UPDATE and S_ISDR; -- JTAG state machine FSM: c4m_jtag_tap_fsm @@ -73,10 +74,12 @@ begin TCK => TCK, TMS => TMS, TRST_N => TRST_N, - STATE => S_STATE, - NEXT_STATE => S_NEXT_STATE, - DRSTATE => S_DRSTATE, - IRSTATE => S_IRSTATE + RESET => S_RESET, + ISIR => S_ISIR, + ISDR => S_ISDR, + CAPTURE => S_CAPTURE, + SHIFT => S_SHIFT, + UPDATE => S_UPDATE ); -- The instruction register @@ -89,10 +92,11 @@ begin TDI => TDI, TDO => IR_TDO, TDO_EN => IR_TDO_EN, - STATE => S_STATE, - NEXT_STATE => S_NEXT_STATE, - IRSTATE => S_IRSTATE, - IR => S_IR + IR => S_IR, + RESET => S_RESET, + CAPTURE => S_CAPTURE and S_ISIR, + SHIFT => S_SHIFT and S_ISIR, + UPDATE => S_UPDATE and S_ISIR ); -- The ID @@ -108,10 +112,10 @@ begin TDI => TDI, TDO => ID_TDO, TDO_EN => ID_TDO_EN, - STATE => S_STATE, - NEXT_STATE => S_NEXT_STATE, - DRSTATE => S_DRSTATE, - IR => S_IR + IR => S_IR, + CAPTURE => S_CAPTURE and S_ISDR, + SHIFT => S_SHIFT and S_ISDR, + UPDATE => S_UPDATE and S_ISDR ); -- The IOS @@ -125,10 +129,10 @@ begin TDI => TDI, TDO => IO_TDO, TDO_EN => IO_TDO_EN, - STATE => S_STATE, - NEXT_STATE => S_NEXT_STATE, - DRSTATE => S_DRSTATE, IR => S_IR, + CAPTURE => S_CAPTURE and S_ISDR, + SHIFT => S_SHIFT and S_ISDR, + UPDATE => S_UPDATE and S_ISDR, CORE_OUT => CORE_OUT, CORE_IN => CORE_IN, CORE_EN => CORE_EN, diff --git a/c4m/vhdl/jtag/c4m_jtag_tap_fsm.vhdl b/c4m/vhdl/jtag/c4m_jtag_tap_fsm.vhdl index 005eccb..fc6ed07 100644 --- a/c4m/vhdl/jtag/c4m_jtag_tap_fsm.vhdl +++ b/c4m/vhdl/jtag/c4m_jtag_tap_fsm.vhdl @@ -14,127 +14,144 @@ entity c4m_jtag_tap_fsm is TRST_N: in std_logic; -- The state outputs - STATE: out TAPSTATE_TYPE; - NEXT_STATE: out TAPSTATE_TYPE; - DRSTATE: out std_logic; - IRSTATE: out std_logic + RESET: out std_logic; + ISDR: out std_logic; + ISIR: out std_logic; + CAPTURE: out std_logic; + SHIFT: out std_logic; + UPDATE: out std_logic ); end c4m_jtag_tap_fsm; architecture rtl of c4m_jtag_tap_fsm is - signal S_STATE: TAPSTATE_TYPE; - signal S_NEXT_STATE: TAPSTATE_TYPE; - signal S_DRSTATE: std_logic; - signal S_IRSTATE: std_logic; - signal NEXT_DRSTATE: std_logic; - signal NEXT_IRSTATE: std_logic; + type TAPSTATE_TYPE is ( + TestLogicReset, + RunTestIdle, + SelectDRScan, + SelectIRScan, + CaptureState, + ShiftState, + Exit1, + Pause, + Exit2, + UpdateState + ); + signal STATE: TAPSTATE_TYPE; + signal DRSTATE: std_logic; + signal IRSTATE: std_logic; + signal NEXT_STATE: TAPSTATE_TYPE; + signal NEXT_DRSTATE: std_logic; + signal NEXT_IRSTATE: std_logic; begin - STATE <= S_STATE; - NEXT_STATE <= S_NEXT_STATE; - DRSTATE <= S_DRSTATE; - IRSTATE <= S_IRSTATE; - + -- Generate outputs from the state + ISDR <= DRSTATE; + ISIR <= IRSTATE; + RESET <= '1' when STATE = TestLogicReset else '0'; + CAPTURE <= '1' when STATE = CaptureState else '0'; + SHIFT <= '1' when STATE = ShiftState else '0'; + UPDATE <= '1' when STATE = UpdateState else '0'; + process (TCK, TRST_N) begin if TRST_N = '0' then - S_DRSTATE <= '0'; - S_IRSTATE <= '0'; - S_STATE <= TestLogicReset; + DRSTATE <= '0'; + IRSTATE <= '0'; + STATE <= TestLogicReset; elsif rising_edge(TCK) then - S_STATE <= S_NEXT_STATE; - S_DRSTATE <= NEXT_DRSTATE; - S_IRSTATE <= NEXT_IRSTATE; + STATE <= NEXT_STATE; + DRSTATE <= NEXT_DRSTATE; + IRSTATE <= NEXT_IRSTATE; end if; end process; NEXT_DRSTATE <= - '0' when S_NEXT_STATE = TestLogicReset else - '0' when S_NEXT_STATE = RunTestIdle else - '1' when S_NEXT_STATE = SelectDRScan else - '0' when S_NEXT_STATE = SelectIRScan else - S_DRSTATE; + '0' when NEXT_STATE = TestLogicReset else + '0' when NEXT_STATE = RunTestIdle else + '1' when NEXT_STATE = SelectDRScan else + '0' when NEXT_STATE = SelectIRScan else + DRSTATE; NEXT_IRSTATE <= - '0' when S_NEXT_STATE = TestLogicReset else - '0' when S_NEXT_STATE = RunTestIdle else - '0' when S_NEXT_STATE = SelectDRScan else - '1' when S_NEXT_STATE = SelectIRScan else - S_IRSTATE; + '0' when NEXT_STATE = TestLogicReset else + '0' when NEXT_STATE = RunTestIdle else + '0' when NEXT_STATE = SelectDRScan else + '1' when NEXT_STATE = SelectIRScan else + IRSTATE; - process (S_STATE, TMS) + process (STATE, TMS) begin - case S_STATE is + case STATE is when TestLogicReset => if (TMS = '0') then - S_NEXT_STATE <= RunTestIdle; + NEXT_STATE <= RunTestIdle; else - S_NEXT_STATE <= TestLogicReset; + NEXT_STATE <= TestLogicReset; end if; when RunTestIdle => if (TMS = '0') then - S_NEXT_STATE <= RunTestIdle; + NEXT_STATE <= RunTestIdle; else - S_NEXT_STATE <= SelectDRScan; + NEXT_STATE <= SelectDRScan; end if; when SelectDRScan => if (TMS = '0') then - S_NEXT_STATE <= Capture; + NEXT_STATE <= CaptureState; else - S_NEXT_STATE <= SelectIRScan; + NEXT_STATE <= SelectIRScan; end if; when SelectIRScan => if (TMS = '0') then - S_NEXT_STATE <= Capture; + NEXT_STATE <= CaptureState; else - S_NEXT_STATE <= TestLogicReset; + NEXT_STATE <= TestLogicReset; end if; - when Capture => + when CaptureState => if (TMS = '0') then - S_NEXT_STATE <= Shift; + NEXT_STATE <= ShiftState; else - S_NEXT_STATE <= Exit1; + NEXT_STATE <= Exit1; end if; - when Shift => + when ShiftState => if (TMS = '0') then - S_NEXT_STATE <= Shift; + NEXT_STATE <= ShiftState; else - S_NEXT_STATE <= Exit1; + NEXT_STATE <= Exit1; end if; when Exit1 => if (TMS = '0') then - S_NEXT_STATE <= Pause; + NEXT_STATE <= Pause; else - S_NEXT_STATE <= Update; + NEXT_STATE <= UpdateState; end if; when Pause => if (TMS = '0') then - S_NEXT_STATE <= Pause; + NEXT_STATE <= Pause; else - S_NEXT_STATE <= Exit2; + NEXT_STATE <= Exit2; end if; when Exit2 => if (TMS = '0') then - S_NEXT_STATE <= Shift; + NEXT_STATE <= ShiftState; else - S_NEXT_STATE <= Update; + NEXT_STATE <= UpdateState; end if; - when Update => + when UpdateState => if (TMS = '0') then - S_NEXT_STATE <= RunTestIdle; + NEXT_STATE <= RunTestIdle; else - S_NEXT_STATE <= SelectDRScan; + NEXT_STATE <= SelectDRScan; end if; when others => - S_NEXT_STATE <= TestLogicReset; + NEXT_STATE <= TestLogicReset; end case; end process; end rtl; diff --git a/test/cocotb/controller/Makefile b/test/cocotb/controller/Makefile index 08b5659..f4e9721 100644 --- a/test/cocotb/controller/Makefile +++ b/test/cocotb/controller/Makefile @@ -22,6 +22,7 @@ TOPLEVEL_LANG=vhdl MODULE=test SIM=ghdl GPI_IMPL=vhpi +GHDL_ARGS=--std=08 SIM_ARGS=--wave=test.ghw COCOTBMAKEFILESDIR=$(shell cocotb-config --makefiles) diff --git a/test/cocotb/dual_parallel/Makefile b/test/cocotb/dual_parallel/Makefile index 383a1ba..8929ddb 100644 --- a/test/cocotb/dual_parallel/Makefile +++ b/test/cocotb/dual_parallel/Makefile @@ -23,6 +23,7 @@ TOPLEVEL_LANG=vhdl MODULE=test SIM=ghdl GPI_IMPL=vhpi +GHDL_ARGS=--std=08 SIM_ARGS=--wave=test.ghw COCOTBMAKEFILESDIR=$(shell cocotb-config --makefiles) diff --git a/test/cocotb/dual_parallel/dual_parallel.vhdl b/test/cocotb/dual_parallel/dual_parallel.vhdl index 989d15a..870ea10 100644 --- a/test/cocotb/dual_parallel/dual_parallel.vhdl +++ b/test/cocotb/dual_parallel/dual_parallel.vhdl @@ -43,9 +43,9 @@ begin TDO => I1_TDO, TRST_N => I1_TRST_N, RESET => open, - DRCAPTURE => open, - DRSHIFT => open, - DRUPDATE => open, + CAPTURE => open, + SHIFT => open, + UPDATE => open, IR => open, CORE_IN => open, CORE_EN => "1", @@ -63,9 +63,9 @@ begin TDO => I2_TDO, TRST_N => I2_TRST_N, RESET => open, - DRCAPTURE => open, - DRSHIFT => open, - DRUPDATE => open, + CAPTURE => open, + SHIFT => open, + UPDATE => open, IR => open, CORE_IN => open, CORE_EN => "1", diff --git a/test/rtl/vhdl/idcode.vhdl b/test/rtl/vhdl/idcode.vhdl index 550df98..cc7d167 100644 --- a/test/rtl/vhdl/idcode.vhdl +++ b/test/rtl/vhdl/idcode.vhdl @@ -50,9 +50,9 @@ begin TDO => TDO, TRST_N => TRST_N, RESET => open, - DRCAPTURE => open, - DRSHIFT => open, - DRUPDATE => open, + CAPTURE => open, + SHIFT => open, + UPDATE => open, IR => open, CORE_OUT => "0", CORE_IN => open, -- 2.30.2